Physical Design Engineer (AI)

Location: Palo Alto, California, United States; onsite

Salary: $250,000–$400,000 per year

Company

hirify.global is an early-stage, venture-backed AI semiconductor startup developing a specialized accelerator and software stack for large language model inference.

What you will do

• Contribute to floorplanning and physical implementation of complex digital ASIC designs.
• Analyze and optimize power, performance, and area trade-offs.
• Identify physical constraints requiring RTL or architectural changes.
• Investigate and resolve floorplanning, timing, power, and design-closure issues.
• Collaborate with RTL, microarchitecture, architecture, and implementation teams, including external implementation partners.
• Support physical verification, implementation signoff, issue closure, and tapeout readiness.

Requirements

• Substantial hands-on experience in digital ASIC physical design and backend implementation.
• Ownership of meaningful physical implementation work on complex ASIC or SoC designs.
• Strong understanding of floorplanning, placement, connectivity, timing constraints, and physical design optimization.
• Experience analyzing power, performance, and area trade-offs and resolving challenging floorplanning, power, timing, or design-closure issues.
• Understanding of how RTL and microarchitecture decisions affect backend implementation feasibility.
• Experience collaborating with RTL, architecture, and physical implementation teams.
• Senior-level technical judgment with a willingness to remain deeply hands-on in physical design and debugging.

Nice to have

• Experience with AI accelerators, inference ASICs, GPUs, or other high-performance compute processors.
• Familiarity with synthesis-to-layout implementation flows.
• Experience with static timing analysis, timing closure, and physical optimization.
• Knowledge of power integrity, power distribution networks, and physical verification.
• Involvement in successful ASIC or SoC tapeouts.
• Experience with external backend design or implementation partners.
• Background in first-generation silicon development or early-stage semiconductor startups.

Culture & Benefits

• Hands-on ownership of physical implementation for first-generation silicon.
• Close collaboration across architecture, RTL, and backend design.
• Opportunity to influence design decisions early and contribute to a first tapeout.

Hiring process

• Typically includes two to three conversations focused on previous technical projects, physical design experience, and engineering problem-solving.
• References may be requested.
• Further company, technology, and roadmap details are shared under NDA as the process progresses.