Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Это senior-роль с высокой ответственностью за floorplanning современных ASIC в крупной полупроводниковой компании и понятной технической областью, но порог в 10-12 лет опыта делает возможность узкоспециализированной.
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Текст:
Hirify AI/Оригинал
TL;DR
ASIC Design - Floorplan Engineer (AI): Defining and optimizing chip-level physical architecture and die layouts for advanced CMOS ASICs used in AI, computing, networking, cellular, and storage products with an accent on floorplanning, macro placement, power delivery, clock planning, and PPA optimization. Focus on timing closure, congestion analysis, ECO implementation, physical verification, IR/EM analysis, and design-flow automation for 3 nm and smaller process technologies.
hirify.global's Custom Silicon Design Team develops custom CMOS ASICs for AI, cellular, networking, computing, and storage products.
What you will do
Define and optimize top-level floorplan architecture, including die-size estimation, hierarchy, partitioning, macro placement, pin placement, and feedthroughs.
Design power grids and plan clock distribution while balancing performance, power, and area targets with RTL, timing, and packaging teams.
Lead top-level timing closure, congestion analysis, ECO implementation, and tapeout readiness.
Coordinate block owners and integration teams to achieve block-to-top-level convergence.
Provide physical-design guidance to internal and external partners and contribute to flow automation and methodology development.
Apply block PnR, timing closure, physical verification, and IR/EM analysis to achieve signoff-quality results.
Requirements
BS in Electrical or Computer Engineering with 12+ years of relevant experience, or MS in Electrical or Computer Engineering with 10+ years of relevant experience.
Strong foundation in VLSI design principles and ASIC physical-design fundamentals.
In-depth experience with floorplanning, die partitioning, and hierarchical design.
Working knowledge of PLLs, clock networks, power delivery, and timing-critical structures.
Proven ability to optimize performance, power, and area through layout and planning strategies.
Strong experience with TCL scripting and Linux environments is required.
Excellent communication, organizational, problem-solving, data-presentation, and prioritization skills, with the ability to work independently across global sites and time zones.
Ability to provide technical leadership, mentor others, and lead new initiatives.
Nice to have
Proficiency in Python, Perl, or Ruby.
Experience with Cadence or equivalent physical-design tools.
Culture & Benefits
Full-time position within a cross-functional engineering organization supporting internal and external partners.
Medical, dental, and vision plans.
401(k) participation with company matching, ESPP, EAP, paid holidays, paid sick leave, vacation, and applicable paid family and other leave.
Eligibility for a discretionary annual bonus, competitive new-hire equity grants, and annual equity awards subject to plan documents and award agreements.
Hiring process
First-time applicants must create a candidate login account before applying; existing candidates must sign in before applying.
Applicants located outside the USA must provide a home address for future correspondence.
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