Senior Physical Design Engineer (AI/ASIC)

Location: San Jose, California, United States; onsite role

Annual base salary: USD 121,900–195,000

Company

hirify.global's ASIC Products Division develops custom high-performance silicon solutions for hyperscale cloud providers, AI companies, and networking infrastructure leaders.

What you will do

• Lead block-level and top-level physical design implementation from floorplanning through GDSII stream-out using Cadence Innovus.
• Execute placement, clock-tree synthesis, routing, and timing and power optimization on 5nm, 3nm, and 2nm technology nodes.
• Perform MCMM static timing analysis, signal integrity optimization, and power-grid signoff including static and dynamic IR-drop and electromigration analysis.
• Drive physical design for next-generation AI and PCIe switch products from RTL to silicon tape-out.
• Automate physical design flows and database manipulation using Tcl, Python, and Unix shell scripting.
• Provide technical leadership, solve complex implementation problems, and collaborate cross-functionally.

Requirements

• B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 8+ years of hands-on physical design experience with successful tape-outs of complex, high-frequency, ultra-large-scale networking or AI ASICs.
• Direct tape-out experience with TSMC advanced nodes N7, N5, and N3, or equivalent foundry processes.
• High proficiency with Cadence Innovus for place-and-route.
• High proficiency with Synopsys PrimeTime or Cadence Tempus for timing and static timing analysis.
• Experience with StarRC or QRC for extraction and RedHawk for IR/EM analysis.
• Experience with Siemens Calibre for DRC/LVS.
• Advanced Tcl, Python, and Unix shell scripting skills.
• Excellent technical leadership, problem-solving, and cross-functional communication skills.

Nice to have

• Strong background in high-speed clock network implementation, including H-tree, mesh, and low-power clock-tree synthesis.
• Experience with power-aware implementation flows, including UPF/CPF, multi-voltage domains, and clock or power gating.

Culture & Benefits

• Discretionary annual bonus and competitive new-hire and annual equity awards, subject to applicable plan documents.
• Medical, dental, and vision plans.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Employee Assistance Program, company-paid holidays, paid sick leave, vacation time, and applicable paid family leave.
• Equal opportunity employment consideration in accordance with federal, state, and local law.