pythonteam leadershipasicfpgasocsystemveriloguvmlow power designdesign verification
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Роль дает серьезную ответственность за верификацию сложных FPGA и ASIC в известной полупроводниковой компании, но динамичная рабочая среда и высокие требования к руководящему опыту подойдут не всем.
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Hirify AI/Оригинал
TL;DR
Manager, Design Engineering (Design Verification) (FPGA/SOC): Leading verification of complex FPGA and ASIC designs by architecting reusable UVM test benches, integrating IP-level and subsystem environments, and driving coverage-based verification through silicon bring-up with an accent on high-speed protocols, low-power architecture, and HW/FW interaction. Focus on leading DV teams, integrating complex multi-instance VIPs to SOC level, solving coverage and debug challenges, and improving verification methodologies for state-of-the-art programmable logic systems.
Location: Penang, Malaysia; candidates must provide proof of their right to work in Malaysia.
Company
Develops low-cost, low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices, with an international engineering and manufacturing organization.
What you will do
Lead and contribute to design verification for complex FPGA and ASIC designs from concept through tape-out and silicon bring-up.
Create coverage-driven verification plans, IP-level and subsystem test benches, portable test benches, sequences, and test infrastructure.
Architect reusable UVM-based test benches and integrate multi-instance VIPs, subsystem environments, and test suites at SOC level.
Verify protocols and subsystems including DDR SDRAM, AMBA interconnect, Ethernet, DisplayPort, MIPI, HDMI, SDI, JESD204B, and PCIe.
Collaborate with design, architecture, software, firmware, and external IP delivery teams to integrate and verify FPGA designs.
Improve verification quality through new tools, methodologies, coverage analysis, hardware validation, and debug.
Requirements
BS or MS degree in Electrical or Computer Engineering, Computer Science, or a related field.
8+ years of dedicated hands-on FPGA or SOC ASIC design verification experience, including at least 5 years leading a DV team verifying complex FPGA or ASIC designs.
Proven experience with full ASIC verification from concept through tape-out to silicon bring-up.
Advanced knowledge of SystemVerilog and UVM methodology.
Experience with C/C++, Perl, Python, or Tcl for design verification automation.
Experience verifying DDR SDRAM, AMBA-based on-chip interconnect, Ethernet, video interfaces, JESD204B, and PCIe subsystems.
In-depth experience with low-power design, UPF integration, boot-up, power cycling, and hardware/firmware interaction verification.
Strong team leadership, interpersonal, communication, problem-solving, and cross-functional collaboration skills.
Nice to have
Experience in hardware validation and debug.
Culture & Benefits
Work in a fast-paced, results-oriented, team-first environment focused on R&D, product innovation, and customer service.
Collaborate with international product development teams on programmable logic solutions used by customers worldwide.
Access a comprehensive compensation and benefits program.
Employment is subject to successful background and reference checks.
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