digital designsocsystemveriloguvmsynthesisrtl designtiming analysispower optimizationovm
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
Пожаловаться
Зарплата и рынок
развернуть
По международному рынку данных пока нет
На СНГ рынке: $1.4к/мес ($1.2к - $2.1к)
88
Крутая вакансия
развернуть
Чётко очерченная роль в разработке SoC у крупного производителя чипов даёт практический опыт с RTL, интеграцией IP и качеством чипа; явных проблем с объёмом обязанностей нет.
Актуальные технологии
Понятные задачи
Масштаб Company hidden
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Подключить Plus
Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Logic Design Engineer (SoC): Developing RTL designs and integrating high-performance IPs for next-generation Client SoCs with an accent on functional integrity, performance, and chip quality. Focus on validating synthesizability, timing and power convergence, netlist quality, functional equivalence, and secure design practices.
Location: On-site in Penang, Malaysia; Shift 1 (Malaysia).
Company
hirify.global's Silicon and Platform Engineering Group develops semiconductor solutions and Client System-on-Chip products.
What you will do
Develop RTL designs for internal IPs and integrate high-performance, bandwidth-intensive IPs into SoCs.
Collaborate with verification teams on functional, feature, and integration validation.
Perform RTL static analysis, synthesizability assessments, timing and power convergence, netlist quality verification, and functional equivalence validation.
Work with design teams, architects, and IP providers to ensure functional integrity, performance, chip quality, and successful IP/SoC handoff.
Develop design optimizations, contribute to cross-functional reviews, and apply secure development practices addressing security threat models.
Requirements
Bachelor's degree in Electrical and Electronics Engineering, Computer Engineering, Computer Science, or a related field plus 3+ years of hands-on SoC RTL/Logic Design experience demonstrated through internships, academic projects, coursework, or hands-on training; alternatively, a relevant Master's degree with no prior professional experience.
Proficiency in RTL design languages such as SystemVerilog.
Basic understanding of digital design, including timing analysis, power optimization, and synthesis techniques.
Familiarity with verification methodologies such as OVM or UVM.
Nice to have
Experience with logic design, high-performance IP integration, or pre-silicon validation environments.
Knowledge of industry-standard tools for RTL simulation, synthesis, and static timing analysis.
Strong problem-solving and communication skills in a collaborative environment.
Culture & Benefits
Full-time experienced-hire position with on-site work required.
Collaborative, cross-functional work across design, architecture, verification, and IP-provider teams.
hirify.global follows responsible and ethical hiring practices and does not charge recruitment or employment-related fees.
All qualified applicants receive consideration without discrimination under applicable local law.
Будьте осторожны
Если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого. Это мошенники. Обязательно жмите «Пожаловаться» или пишите в поддержку. Подробнее в гайде →