pythongittclsemiconductorplace and routefinfetcadence innovusadvanced nodesdual patterningulv
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
Пожаловаться
Зарплата и рынок
ЗП не указана
На похожих ролях по рынку
$168к$177кмедиана$188к
50 в выборке
На СНГ рынке: $2.5к/мес ($1.9к - $3.1к)
84
Хорошая вакансия
развернуть
В Company hidden хорошо очерчена роль в CAD для полупроводников: работа с передовыми техпроцессами и влияние на общую инфраструктуру компании. При этом работа только из офиса и ограничения экспортного контроля сужают круг тех, кому она доступна.
Кликните для подробной информации
Ограничения по допускуАктуальный инструментарийЧёткие задачиВлияние на полупроводники
Оценка от Hirify AI
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Подключить Plus
Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Staff CAD Engineer (Cadence Innovus): Developing and maintaining automated place-and-route flows and add-on tools for advanced semiconductor design with an accent on CAD infrastructure, methodology, and flow integration. Focus on enabling 7nm-and-below technologies, solving FinFET, dual-patterning, and ultra-low-voltage challenges, and supporting EDA tool deployment.
Location: Austin, TX, United States; onsite role
Expected base pay range: $0–$0 per annum, plus eligibility for bonus and equity plans.
Company
hirify.global develops semiconductor solutions and data-infrastructure technologies for enterprise, cloud, AI, and carrier architectures.
What you will do
Develop and maintain automated place-and-route flows for multiple business units.
Deploy, support, and integrate flows within the broader CAD platform.
Develop add-on tools and innovative solutions for evolving semiconductor design challenges.
Enable new process technologies and tools in design execution flows.
Generate, centralize, and share knowledge about place-and-route methodology.
Collaborate with EDA vendors to optimize tool usage.
Requirements
Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 3–5 years of related professional experience; alternatively, a Master’s degree and/or PhD with 2–3 years of experience, or equivalent professional experience in lieu of a formal degree.
At least 2 years of recent experience with Cadence Innovus.
Proven tape-out experience on advanced nodes of 7nm or below, with familiarity with FinFET, dual patterning, and ULV challenges.
Good scripting skills in Tcl and Python for flow development.
Experience with revision-control tools such as Git.
Strong analysis, problem-solving, out-of-the-box thinking, verbal communication, written communication, and teamwork skills.
Applicants must be eligible to access export-controlled information under U.S. export control laws. Applicants other than U.S. citizens, lawful permanent residents, or protected individuals may be subject to an export license review before employment.
Culture & Benefits
Work as part of hirify.global Central Engineering on organization-wide CAD infrastructure, methodology, and workflows.
Benefits support financial well-being, family support, mental and physical health, and recognition.
Benefits include an employee stock purchase plan with a two-year lookback, family support programs, mental health resources, recognition awards, bonus participation, and equity plans.
AI tools, transcription apps, real-time answer generators, and automated note-taking bots are prohibited during interviews; unauthorized use results in disqualification.
Hiring process
Applicants requiring reasonable accommodation during selection should contact the hirify.global HR Helpdesk.
Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →