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3 дня назад

Staff / Principal ASIC Design Engineer

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Israel
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Текст:
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TL;DR
Staff / Principal ASIC Design Engineer (ASIC/AI infrastructure): Designing complex digital ASIC blocks for high-performance AI connectivity systems with an accent on micro-architecture, RTL implementation, and PPA optimization. Focus on solving deep-submicron logic challenges, supporting backend implementation, and improving verification, timing, power, and design automation workflows.

Location: Haifa District, Israel; other location: Israel

Company

hirify.global develops connectivity solutions for rack-scale AI infrastructure, integrating CXL, Ethernet, NVLink, PCIe, UALink, and the COSMOS software suite.

What you will do

  • Own digital logic blocks from high-level definition and micro-architecture through RTL coding, debug, and backend implementation support.
  • Transform complex logic requirements into high-performance hardware solutions and serve as the point of contact for assigned blocks.
  • Collaborate with Architecture, Verification, and Backend teams to integrate designs.
  • Use lint, CDC, synthesis, timing, power, and internal quality-assurance tools to deliver robust, scalable, and power-efficient designs.
  • Apply PPA techniques, contribute to verification and validation, and support design methodology and tool-automation improvements.
  • Use AI assistance tools and contribute to in-house automation development.

Requirements

  • Bachelor’s degree in Electrical Engineering or a related technical field.
  • 5+ years of logic-design experience at semiconductor companies.
  • Knowledge and experience with Verilog and/or SystemVerilog.
  • Understanding of digital design principles and RTL coding best practices.
  • Excellent communication skills and the ability to work effectively across teams.

Nice to have

  • Master’s degree in Electrical Engineering or a related field.
  • Knowledge of DDR and PCIe protocols and implementation.
  • Understanding of power-management techniques for low-power design.
  • Familiarity with clock-domain crossing, simulation, debugging, synthesis, and timing analysis.
  • Proficiency in Python or Perl scripting.
  • Experience with high-speed serial-interface designs or connectivity protocols.

Culture & Benefits

  • Join a new strategic R&D center in Israel focused on semiconductor chips for AI infrastructure.
  • Work in a diverse environment that encourages applications from people with varied backgrounds and experiences.
  • Collaborate across engineering disciplines while contributing to a local engineering organization being built from the ground up.

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