Design Verification Intern (SystemVerilog/UVM)

Location: Petah Tikva, Israel

Company

hirify.global develops semiconductor solutions for enterprise, cloud, AI, and carrier data infrastructure, including next-generation network switches.

What you will do

• Implement new design and verification features for network-switch products.
• Write verification test plans using random techniques and coverage analysis.
• Develop object-oriented random verification environments with SystemVerilog and UVM.
• Create tests, tune verification environments, and close code and functional coverage goals.
• Debug simulation failures to identify root causes and investigate new protocols and features.
• Use scripting languages to automate repetitive tasks and improve efficiency while targeting high-frequency, high-performance, and low-power designs.

Requirements

• Currently pursuing a B.S. or M.S. degree in Computer Science, Electrical Engineering, or a related technical field.
• At least 1.5 years remaining until graduation.
• Good understanding of object-oriented programming and digital logic.
• Excellent problem-solving skills.
• Strong interpersonal skills and the ability to work effectively in a team.

Nice to have

• No optional qualifications were specified.

Culture & Benefits

• Full-time employment in a collaborative, transparent, and inclusive environment.
• Access to tools and resources for professional growth and development.
• Competitive compensation and benefits.
• Interview assistance through AI tools, transcription apps, automated note-taking bots, and similar tools is prohibited.
• Employment may require eligibility to access export-controlled technology and may involve a U.S. export license review.