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3 дня назад

Staff Physical Design Engineer - SoC EMIR Engineer (AI Semiconductors)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Israel
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Текст:
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TL;DR
Staff Physical Design Engineer - SoC EMIR Engineer (AI Semiconductors): Developing and signing off EMIR and power-integrity methodologies for complex SoCs in advanced FinFET nodes with an accent on voltage-drop analysis, electromigration, and chip-package co-analysis. Focus on diagnosing power violations, balancing signal and power-grid EM, and ensuring reliability and yield for high-performance AI connectivity silicon.

Location: Haifa District, Israel; other location: Israel

Company

hirify.global develops rack-scale AI infrastructure and semiconductor connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, and UALink with its COSMOS software suite.

What you will do

  • Perform IR-drop analysis and signal- and power-electromigration analysis for complex SoCs.
  • Collaborate with Physical Design engineers to ensure full power integrity.
  • Partner with Package Design engineers on chip-package co-analysis.
  • Identify root causes of voltage-drop violations and electromigration risks.
  • Execute backend power methodologies for high-performance connectivity silicon and support voltage-drop and reliability targets.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering or a related technical field.
  • 7+ years of hands-on EMIR or power-integrity analysis experience for high-performance SoCs or high-speed connectivity products.
  • Strong proficiency with industry-standard EMIR tools, including Ansys RedHawk/RedHawk-SC or Cadence Voltus.
  • Deep understanding of EM/IR challenges in advanced 7nm, 5nm, or 3nm FinFET process nodes.
  • Deep understanding of Place & Route flows, power-grid synthesis, RC extraction, and standard-cell architecture.
  • Deep understanding of electromigration and the trade-offs between signal EM and power-grid EM.

Nice to have

  • Familiarity with thermal-analysis tools and their interaction with electrical performance.
  • Experience with sign-off criteria and margins for high-volume production chips.
  • Good understanding of timing and P&R.
  • Basic understanding of packaging, top-metal layers, MIM capacitor usage, and power distribution.
  • Ability to write TCL scripts for STA and Fusion Compiler.

Culture & Benefits

  • Join a new strategic R&D center in Israel and take meaningful technical ownership at a site being built from the ground up.
  • Work on chips supporting large-scale AI and cloud environments.
  • The company encourages applications from people with diverse backgrounds and experiences, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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