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3 дня назад

Senior ASIC Design Engineer (AI Infrastructure)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Israel
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Senior ASIC Design Engineer (AI Infrastructure): Designing complex digital ASIC blocks for AI infrastructure connectivity from high-level definition through RTL implementation and backend support with an accent on micro-architecture, high-performance hardware, and PPA optimization. Focus on solving deep-submicron logic challenges, applying EDA-based quality checks, and collaborating across architecture, verification, and backend teams.

Location: Haifa District, Israel; other location: Israel

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, UALink, and the COSMOS software suite.

What you will do

  • Own digital logic blocks from high-level definition and micro-architecture through RTL coding, debugging, and backend implementation support.
  • Transform complex logic challenges into high-performance hardware and serve as the point of contact for assigned blocks.
  • Use Lint, CDC, synthesis, timing, power, and internal quality-assurance tools to deliver robust, scalable, power-efficient designs.
  • Apply techniques to meet PPA targets and contribute to verification and validation activities.
  • Improve design methodologies, develop tool automation, and use AI assistance tools to accelerate engineering workflows.
  • Collaborate with Architecture, Verification, Backend, and other engineering teams.

Requirements

  • Bachelor’s degree in Electrical Engineering or a related technical field.
  • 3+ years of experience in logic design at semiconductor companies.
  • Knowledge and experience with Verilog and/or SystemVerilog.
  • Understanding of digital design principles and RTL coding best practices.
  • Excellent communication skills and ability to work effectively across teams.

Nice to have

  • Master’s degree in Electrical Engineering or a related field.
  • Knowledge of DDR and PCIe protocols and implementation.
  • Understanding of power-management techniques for low-power design.
  • Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis.
  • Proficiency in Python or Perl scripting.
  • Experience with high-speed serial interface designs or connectivity protocols.

Culture & Benefits

  • Join a new strategic R&D center in Israel focused on complex semiconductor chips for AI infrastructure.
  • Work in a newly established engineering site with meaningful product ownership and cross-functional collaboration.
  • The company encourages applications from people with diverse backgrounds and experiences, including veterans, parents, people with disabilities, people of color, and LGBTQ+ and non-binary people.

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