Sr. Principle VLSI/ASIC Design Engineer (ASIC)

Location: Hybrid in Sunnyvale, California, United States; work from an HPE office an average of 2 days per week.

Base salary: USD 181,000–367,000 annually in California, United States. Variable incentives may also be offered.

Company

hirify.global is an edge-to-cloud technology company developing infrastructure and solutions for data, networking, compute, and applications.

What you will do

• Lead early-stage ASIC architecture and design exploration for complex networking, compute, and SoC applications.
• Define architectures, microarchitectures, design methodologies, and implementation plans aligned with product requirements and technology roadmaps.
• Design and modify complex RTL blocks, driving implementation through synthesis, physical design support, timing closure, and production readiness.
• Analyze performance, power, area, scalability, reliability, cost, risk, and schedule tradeoffs through modeling, simulation, prototyping, and experimental evaluation.
• Conduct design reviews, establish integration plans, and contribute to organization-wide ASIC architectures, methodologies, and standards.
• Collaborate with architecture, hardware, firmware, verification, physical design, systems, software, manufacturing, suppliers, and external development teams; mentor engineers and provide technical direction.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; equivalent experience may be considered.
• Typically 11 or more years of experience in ASIC, VLSI, SoC, or related hardware design.
• Demonstrated experience designing complex RTL blocks for networking, compute, communications, storage, or other advanced SoC applications.
• Experience leading architecture and design exploration through RTL implementation and product integration.
• Advanced knowledge of ASIC and VLSI design principles, digital logic, RTL design, and SoC development.
• Proven experience developing complex RTL using Verilog, SystemVerilog, or comparable hardware description languages.
• Understanding of ASIC development flows, including architecture, microarchitecture, RTL coding, synthesis, timing analysis, physical design interaction, and design signoff.
• Experience with design modeling, simulation, performance analysis, empirical evaluation, and improving design methodologies, tools, automation, and engineering practices.
• Strong analytical, problem-solving, technical decision-making, written and verbal communication, collaboration, and influence skills, including communication with technical and executive audiences.
• Ability to work across geographically distributed, cross-functional teams and mentor engineers without direct management responsibility.

Nice to have

• Design verification experience, including formal verification, constrained-random verification, coverage methodologies, or verification planning.
• Experience with networking ASICs, data-processing units, switching, routing, acceleration, storage, or high-performance computing architectures.
• Experience with high-speed interfaces, packet-processing pipelines, memory subsystems, interconnects, or performance-critical datapaths.
• Experience with low-power design, clock-domain crossing, reset-domain crossing, DFT, and design-for-reuse methodologies.
• Knowledge of industry standards and leading-edge ASIC implementation technologies.
• Experience working with outsourced development partners, IP vendors, foundries, or semiconductor suppliers.

Culture & Benefits

• Health, financial, and emotional wellbeing benefits for employees and their loved ones.
• Personal and professional development programs supporting career growth and knowledge expertise.
• Inclusive workplace that values varied backgrounds and individual uniqueness.
• Hybrid flexibility designed to support work and personal needs.
• Accessibility accommodations are available during the application and interview process.