pythonc++cfpgapower analysislow power designrtlstatic timing analysispower optimizationpower aware synthesis
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Средняя
$220к/год
$160к$200кмедиана$220к
По похожим ролям (50) ~ $200к/год
На СНГ рынке: $2.5к/мес ($1.9к - $3.1к)
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Хорошая вакансия
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Это хорошо очерченная senior-роль в зрелой продуктовой компании по FPGA с заметной технической ответственностью; требование права на работу в США сужает круг доступных возможностей.
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Только с правом на работу в СШАСильная экспертиза в FPGAПродуктовая компания
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Текст:
Hirify AI/Оригинал
TL;DR
Senior System Power Architect (FPGA): Driving power analysis and low-power optimization across FPGA hardware and software with an accent on power modeling, RTL methodology, and power-performance analysis. Focus on developing chip-level estimation models, correlating simulations with silicon, and aligning cross-functional hardware and software roadmaps.
Location: San Jose, CA, United States. Right to work in the United States is required.
Base pay: $220,000; additional variable or incentive compensation and/or equity may be available.
Company
hirify.global develops programmable logic solutions, including FPGA, CPLD, and programmable power management devices, with a global workforce focused on product innovation and customer success.
What you will do
Define low-power feature specifications, user flows, algorithms, and methodologies while aligning software, marketing, and applications teams.
Drive power-performance analysis to influence hardware and software roadmaps.
Develop chip-level power estimation models covering dynamic, static, clock, memory, and I/O power, and correlate models with simulations and silicon.
Establish power-aware RTL methodology and develop power and competitive benchmarks.
Lead and mentor junior engineers across distributed teams.
Requirements
BS, MS, or PhD in EE, CE, CS, or a related field with 8+ years of relevant experience for BS, 6+ years for MS, or 3+ years for PhD.
Strong knowledge of low-power design techniques.
Deep expertise in RTL and gate-level power analysis and optimization, power-aware synthesis, and place-and-route.
Hands-on experience with industry power and timing tools such as PrimePower, PrimeTime, SpyGlass, Joules, Voltus, or PowerArtist, with strong knowledge of STA and power/timing ECO flows.
Proficiency in C, C++, and Python.
Strong written and verbal communication skills and the ability to drive cross-functional alignment.
Successful background and reference checks and satisfactory proof of the right to work in the United States are required.
Nice to have
Knowledge of FPGA architecture, design flows, and use cases.
Culture & Benefits
Full-time position in a fast-paced, results-oriented, team-first environment.
Comprehensive benefits may include healthcare, retirement plans, and paid time off.
Variable or incentive compensation and/or equity may be available in addition to base pay.
Pay varies according to job-related knowledge, skills, experience, and work location within the U.S. market.
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