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5 дней назад

Senior System Power Architect (FPGA)

220 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Текст:
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TL;DR
Senior System Power Architect (FPGA): Driving power analysis and low-power optimization across FPGA hardware and software with an accent on power modeling, RTL methodology, and power-performance analysis. Focus on developing chip-level estimation models, correlating simulations with silicon, and aligning cross-functional hardware and software roadmaps.

Location: San Jose, CA, United States. Right to work in the United States is required.

Base pay: $220,000; additional variable or incentive compensation and/or equity may be available.

Company

hirify.global develops programmable logic solutions, including FPGA, CPLD, and programmable power management devices, with a global workforce focused on product innovation and customer success.

What you will do

  • Define low-power feature specifications, user flows, algorithms, and methodologies while aligning software, marketing, and applications teams.
  • Drive power-performance analysis to influence hardware and software roadmaps.
  • Develop chip-level power estimation models covering dynamic, static, clock, memory, and I/O power, and correlate models with simulations and silicon.
  • Establish power-aware RTL methodology and develop power and competitive benchmarks.
  • Lead and mentor junior engineers across distributed teams.

Requirements

  • BS, MS, or PhD in EE, CE, CS, or a related field with 8+ years of relevant experience for BS, 6+ years for MS, or 3+ years for PhD.
  • Strong knowledge of low-power design techniques.
  • Deep expertise in RTL and gate-level power analysis and optimization, power-aware synthesis, and place-and-route.
  • Hands-on experience with industry power and timing tools such as PrimePower, PrimeTime, SpyGlass, Joules, Voltus, or PowerArtist, with strong knowledge of STA and power/timing ECO flows.
  • Proficiency in C, C++, and Python.
  • Strong written and verbal communication skills and the ability to drive cross-functional alignment.
  • Successful background and reference checks and satisfactory proof of the right to work in the United States are required.

Nice to have

  • Knowledge of FPGA architecture, design flows, and use cases.

Culture & Benefits

  • Full-time position in a fast-paced, results-oriented, team-first environment.
  • Comprehensive benefits may include healthcare, retirement plans, and paid time off.
  • Variable or incentive compensation and/or equity may be available in addition to base pay.
  • Pay varies according to job-related knowledge, skills, experience, and work location within the U.S. market.

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