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5 дней назад

Senior/Principal Physical Design Engineer (AI)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
UK
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Текст:
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TL;DR
Senior/Principal Physical Design Engineer (AI/ASIC): Implementing complex ASIC and SoC physical designs from synthesis through sign-off, with an accent on PPA optimisation, timing closure, power integrity, and manufacturability. Focus on developing EDA flows, integrating DFT structures, analysing IR drop and signal integrity, and applying AI tools to improve chip design quality.

Location: London - JJ Mack or Bristol - The Crescent, United Kingdom

Company

hirify.global is a semiconductor startup founded in 2022 that develops chips and systems for high-speed inference of frontier AI models.

What you will do

  • Drive end-to-end physical implementation of complex ASIC and SoC designs, including floorplanning, placement, clock tree synthesis, routing, and sign-off, with potential full-chip ownership.
  • Perform synthesis, static timing analysis, timing closure, and PPA optimisation.
  • Develop power plans and analyse IR drop, electromigration, signal integrity, and low-power architectures.
  • Ensure DRC, LVS, formal verification, and other physical verification requirements are met.
  • Collaborate with RTL, architecture, verification, DFT, process technology, foundry, and engineering teams on constraints, manufacturability, yield, and physical-aware RTL.
  • Develop EDA flows and use advanced AI tools and models to improve engineering productivity, analysis, and design quality.

Requirements

  • Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
  • 8+ years of physical design experience for advanced technology nodes, such as 7nm, 5nm, or below.
  • Strong proficiency with EDA tools for place and route, static timing analysis, and sign-off, including tools such as Cadence Innovus, Synopsys Fusion Compiler, and Mentor Graphics Calibre.
  • Solid understanding of CMOS technology, semiconductor physics, and process limitations.
  • Experience with low-power design methodologies, power optimisation, and multi-power-domain architectures.
  • Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
  • Proficiency in scripting languages such as TCL, Perl, or Python for automation.
  • Excellent problem-solving, communication, and teamwork skills in a collaborative design environment.
  • Experience in high-performance computing, AI accelerators, or networking chips.

Nice to have

  • Experience or strong interest in leveraging advanced AI tools and models within the engineering workflow.

Culture & Benefits

  • Competitive salary reflecting experience and the specialist nature of the role.
  • Meaningful equity and ownership participation.
  • Private medical, dental, and vision coverage.
  • Contributory pension, 25 days of holiday plus bank holidays, and life or critical illness insurance.
  • Diverse and inclusive office environment with a commitment to equal employment opportunity.
  • Work involves technologies subject to UK, US, and other international export control regulations; certain roles may require additional eligibility checks.

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