PMTS, PEX Engineer - Quantum (Semiconductor PDK)

Location: Offsite, USA - Massachusetts; travel up to 10%.

Expected salary: $143,000–$247,000 per year.

Company

hirify.global is a full-service semiconductor foundry providing design, development, and fabrication services with manufacturing operations across three continents.

What you will do

• Develop, code, qualify, maintain, and release DRC, LVS, and PEX rule decks and related PDK components.
• Translate process requirements, design rules, device definitions, and electrical models into production-quality physical verification and extraction solutions.
• Build regression tests and qualification methodologies covering correctness, coverage, performance, scalability, and EDA compatibility.
• Analyze and debug complex DRC, LVS, and PEX issues and resolve discrepancies with process, modeling, design, and EDA teams.
• Develop automation and AI/ML-assisted methods for rule generation, test creation, coverage analysis, error classification, anomaly detection, and debugging.
• Optimize verification and extraction flows and drive PDK release readiness through documentation, change management, and continuous improvement.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Microelectronics, Computer Science, Applied Physics, or a related technical field.
• Relevant experience in semiconductor PDK development, physical verification, EDA, IC physical design, parasitic extraction, or a related field, with minimum years aligned to the applicable GF career level.
• Experience with DRC and/or LVS rule development, coding, debugging, or qualification.
• Understanding of parasitic resistance and capacitance extraction, interconnect modeling, layout-dependent effects, and their impact on circuit performance.
• Working knowledge of CMOS process technologies, semiconductor devices, layout design rules, interconnect structures, and design-to-manufacturing interactions.
• Experience with industry-standard physical verification and/or extraction environments and rule-deck development methodologies.
• Experience with Python, Tcl, Perl, shell scripting, or equivalent for engineering automation, regression testing, and data analysis.
• Ability to troubleshoot complex technical problems, perform structured root-cause analysis, and develop robust engineering solutions.
• Written and verbal fluency in English.

Nice to have

• Master’s degree or PhD in a relevant technical field.
• Experience developing and releasing production PDK DRC, LVS, and/or PEX rule decks.
• Experience with Siemens Calibre, Synopsys IC Validator, Cadence Pegasus/PVS, or equivalent tools.
• Experience with PEX technology-file development, RC extraction, process-corner modeling, and silicon/model correlation.
• Experience with automated regression environments, rule coverage metrics, test structures, or PDK qualification methodologies.
• Experience applying AI/ML, generative AI, or data-driven techniques to semiconductor design enablement.
• Understanding of process integration, design rules, OPC/lithography, device modeling, reliability, extraction, and circuit design interactions.
• Experience collaborating with EDA vendors and internal or external design teams.
• Strong written and verbal communication, planning, and organizational skills.

Culture & Benefits

• Full-time employment with a global semiconductor foundry.
• Offsite work arrangement associated with the USA - Massachusetts location.
• Travel may be required up to 10%.
• Employment is subject to applicable pre-employment conditions and laws.
• Reasonable accommodations are available during the employment process.