Senior PDK Physical Verification Engineer (Semiconductor)

Location: Hybrid work model with on-site and off-site work at assigned Intel sites in Hillsboro, Oregon; additional US locations include Santa Clara, California, Austin, Texas, and Phoenix, Arizona.

Salary: Annual salary range of $149,600.00–$284,580.00 USD.

Company

Intel's Design Technology Platform organization develops design-enablement technologies and Process Design Kits for advanced semiconductor products.

What you will do

• Lead the development, implementation, and validation of density-fill solutions within advanced PDKs.
• Develop algorithmic physical-verification solutions using Calibre, Synopsys ICV, and Cadence Pegasus for density compliance and manufacturability.
• Collaborate with process integration teams, design-rule owners, product design engineers, customers, and external EDA vendors.
• Drive automation, scalability, and deployment across multiple design environments.
• Design validation frameworks, test suites, and qualification methodologies for tool and rule-deck releases.
• Develop documentation and training materials, advance physical-verification methodologies, and contribute as a technical expert to the design-enablement roadmap.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with 6+ years of relevant experience; or a Master's degree with 5+ years; or a PhD with 2+ years.
• 4+ years of hands-on experience with at least one industry-standard physical-verification platform such as Calibre, ICV, or Pegasus, including methodology development, rule-deck debugging, validation, or production deployment.
• 3+ years of experience developing, maintaining, or debugging physical-verification rule decks using SVRF, TVF, PXL, PVL, or Tcl-based verification environments.
• Experience with semiconductor process technology, device physics, design rules, manufacturability requirements, and advanced-node physical-design or manufacturing challenges.
• Experience with Unix/Linux operating systems and engineering computing environments.
• Strong communication, technical presentation, problem-solving, debugging, analytical, and technology-scaling skills.

Nice to have

• 4+ years of direct experience developing, deploying, or supporting density-fill methodologies for advanced semiconductor technologies at 16nm and below.
• Expertise in fill-rule implementation, density optimization, manufacturing-driven design methodologies, DRC, density analysis, fill verification, and process-aware design enablement.
• Experience supporting leading foundry, IDM, or advanced process technologies.
• Familiarity with Cadence Virtuoso or Synopsys Custom Designer.
• Experience leading technical initiatives, improving processes, influencing roadmaps, and collaborating with multidisciplinary teams and external partners.
• Prior experience with semiconductor foundries, IDMs, OSATs, or EDA vendors developing physical-verification methodologies, density-fill solutions, PDKs, or design-for-manufacturing technologies.

Culture & Benefits

• Hybrid work model combining on-site work at an assigned Intel site with off-site work.
• Full-time experienced-hire position on Shift 1 in the United States.
• Competitive pay, stock bonuses, health benefits, retirement benefits, and vacation.
• Work on advanced semiconductor-manufacturing challenges with experts across process technology, CAD, physical design, and EDA.