Senior PDK Physical Verification Engineer (Semiconductor)

Location: Hybrid work model across assigned hirify.global sites in Hillsboro, Oregon; Santa Clara, California; Austin, Texas; or Phoenix, Arizona, with time split between on-site and off-site work.

Annual salary range: $149,600.00–$284,580.00 USD.

Company

hirify.global develops advanced semiconductor technologies and design enablement solutions for next-generation products and manufacturing.

What you will do

• Lead the development, implementation, and validation of density-fill solutions within advanced Process Design Kits.
• Develop algorithmic solutions using Calibre, Synopsys ICV, and Cadence Pegasus for density compliance and manufacturability.
• Collaborate with process integration, design-rule, product-design, customer, and external EDA teams to define and deliver solutions.
• Drive automation, scalable deployment, validation frameworks, test suites, and qualification methodologies for tool and rule-deck releases.
• Advance physical-verification methodologies for technology scaling and contribute to design-enablement roadmaps.
• Create technical documentation, training materials, and best practices for hirify.global’s design community.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with 6+ years of relevant experience; or a master’s degree with 5+ years; or a PhD with 2+ years.
• 4+ years of hands-on experience with at least one industry-standard physical-verification platform, including methodology development, rule-deck debugging, validation, or production deployment.
• 3+ years of experience developing, maintaining, or debugging physical-verification rule decks using SVRF, TVF, PXL, PVL, or Tcl-based verification environments.
• Experience with semiconductor process technology, device physics, design rules, manufacturability requirements, and advanced-node physical-design or manufacturing challenges.
• Experience with Unix/Linux operating systems and engineering computing environments.
• Strong communication, technical presentation, problem-solving, debugging, analytical, and cross-functional collaboration skills.

Nice to have

• 4+ years of direct experience developing, deploying, or supporting density-fill methodologies for advanced semiconductor technologies at 16nm and below.
• Expertise in fill-rule implementation, density optimization, DRC, density analysis, fill verification, and process-aware design enablement.
• Experience with leading foundry, IDM, OSAT, EDA, or advanced-process environments.
• Familiarity with Cadence Virtuoso or Synopsys Custom Designer.
• Experience leading technical initiatives, improving processes, or influencing product and methodology roadmaps.

Culture & Benefits

• Hybrid work model combining on-site work at an assigned hirify.global site with off-site work.
• Competitive pay with stock bonuses, health benefits, retirement programs, and vacation.
• Work with experts across process technology, CAD, physical design, and EDA on methodologies used across advanced hirify.global products.
• Full-time experienced-hire position on Shift 1 in the United States.