Advanced Packaging Technology & Integration Leader (Semiconductor Packaging)

Location: Santa Clara, CA, United States. Full-time onsite role; travel required 10% of the time. Relocation eligible.

Salary: $200,000–$275,000 per year, plus potential bonus and stock awards.

Company

hirify.global develops materials science, engineering solutions, and equipment for semiconductor chips and advanced displays, including technologies supporting AI and next-generation semiconductor manufacturing.

What you will do

• Lead development of next-generation semiconductor packaging and 3D integration technologies from first principles through manufacturable solutions.
• Develop technology roadmaps and experimentally testable structures, integration flows, and demonstrations for AI/HPC, memory, and heterogeneous-integration architectures.
• Provide technical leadership across hybrid bonding, TSVs, 2.5D/3D integration, interposers, bridge-die architectures, chiplets, advanced interconnects, thermal management, and interface engineering.
• Develop complete process-integration strategies across deposition, etch, CMP, cleans, bonding, lithography, metallization, wafer thinning, and packaging operations.
• Lead multidisciplinary teams, mentor technical staff, conduct technical reviews, and communicate complex issues to engineering teams and senior executives.
• Engage with logic, memory, foundry, OSAT, and AI/HPC customers, universities, suppliers, equipment partners, and research organizations.

Requirements

• Advanced degree in Materials Science, Chemical Engineering, Electrical Engineering, Mechanical Engineering, Applied Physics, or a closely related discipline preferred, or equivalent demonstrated semiconductor technology-development expertise.
• Demonstrated experience developing semiconductor technologies or integration schemes from early concept through experimental validation, with deep understanding of semiconductor process integration.
• Strong expertise in several of the following: hybrid bonding, TSV technology, 2.5D/3D integration, interposers, bridge die, chiplet integration, thermal-management materials, thin-wafer processing, wafer/die bonding, advanced metallization, CMP and surface preparation, mechanical stress and wafer warpage, and semiconductor/package reliability.
• Ability to reason from fundamental physics and materials behavior, define experiments that distinguish competing physical mechanisms, and accelerate technical learning.
• Strong record of leading complex, multidisciplinary semiconductor technology-development programs and influencing organizations beyond direct reporting relationships.
• Ability to mentor technical teams and communicate effectively from detailed engineering reviews through executive-level technology strategy.

Nice to have

• Experience developing technology for AI/HPC, HBM, chiplets, logic-memory integration, or other high-performance heterogeneous systems.
• Experience across the semiconductor ecosystem, including device manufacturers, foundries, OSATs, equipment companies, material suppliers, or research organizations.
• Experience translating future device and package architectures into semiconductor process and equipment requirements.
• Technical innovation demonstrated through patents, publications, technology transfers, or successful product/process introductions.
• Understanding of interactions among electrical performance, power delivery, thermal management, mechanical integrity, manufacturability, cost, and yield.
• Experience moving technology from pathfinding/R&D into product development or manufacturing.

Culture & Benefits

• Supportive environment focused on learning, development, innovation, and technical growth.
• Comprehensive employee benefits supporting health and wellbeing.
• Potential eligibility for bonus and stock award programs.
• Regular employment with full-time status and travel of 10%.