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10 дней назад

Design Engineer (Custom Layout)

Формат работы
onsite
Тип работы
fulltime
Грейд
middle
Английский
b2
Страна
China
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Design Engineer (Custom Layout): Developing custom layouts and floorplans for analog and high-speed mixed-signal PHY blocks such as SerDes, USB, and DDR with an accent on matching, signal routing, noise reduction, and hierarchy planning. Focus on performing DRC/LVS/ERC and EMIR analysis, solving layout integrity issues, and coordinating with analog circuit design teams.

Location: Shanghai, China; onsite

Company

hirify.global develops technology and tools for electronic design and semiconductor engineering.

What you will do

  • Develop custom layout floorplans, including matching guides, resistor and capacitor placement, coupling and noise reduction, and sensitive and mixed-signal routing.
  • Create top-level custom layout hierarchy floorplans for blocks and power structures.
  • Develop layouts for high-speed mixed-signal PHYs, including SerDes, USB, and DDR.
  • Coordinate with the analog circuit design team to ensure efficient, high-quality analog layout design.
  • Perform DRC/LVS/ERC and EMIR analysis and recommend appropriate solutions.

Requirements

  • BSEE degree and 2+ years of applicable experience in analog or custom layout for advanced technology nodes.
  • Proficiency with layout editing and verification tools, such as Virtuoso XL and Pegasus/Calibre DRC/LVS.
  • Proficiency with EMIR tools such as Voltus-FI.
  • Hands-on experience conducting DRC/LVS/ERC and EMIR analyses and recommending solutions.
  • Fundamental understanding of IC design technology, processes, and methodology.
  • Good teamwork, self-motivation, and communication skills in English.

Nice to have

  • Experience with PERC runs, FinFET layout, ESD/Latch-up, or cooperation with a digital P&R team.

Culture & Benefits

  • Full-time position based onsite in Shanghai, China.
  • Opportunity to contribute to technology-focused semiconductor design work.

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