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Задачи подходят для опытного специалиста по ASIC/SoC, но долгосрочный контракт с обязательной работой в офисе и отсутствие деталей о ставке и конечном заказчике оставляют важные условия неясными.
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Условия контрактаПонятные задачиВысокий порог опыта
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Текст:
Hirify AI/Оригинал
TL;DR
Physical Design Engineer (ASIC/SoC): Driving RTL synthesis, floorplanning, netlist optimization, and timing closure for complex ASIC/SoC designs with an accent on performance, power, area, and implementation efficiency. Focus on optimizing advanced-node physical designs, resolving timing and congestion bottlenecks, and collaborating across RTL, architecture, verification, and physical design teams.
Location: Onsite in Sunnyvale, California, United States
Company
hirify.global Inc is hiring for a long-term contract supporting silicon engineering work for a leading technology organization.
What you will do
Drive RTL synthesis and optimization to meet performance, power, and area goals.
Perform floorplanning for complex ASIC/SoC designs, optimizing timing, congestion, and power distribution.
Analyze netlists and identify opportunities to improve design quality and implementation efficiency.
Support timing closure by identifying implementation bottlenecks and recommending design improvements.
Collaborate with architecture, RTL, verification, and physical design teams throughout design convergence.
Participate in design reviews and improve physical design processes and methodologies.
Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
10+ years of industry experience in ASIC/SoC physical design.
Strong hands-on experience with RTL synthesis and timing optimization.
Solid experience with floorplanning for advanced technology nodes.
Strong understanding of netlist optimization and physical implementation methodologies.
Experience collaborating with RTL/design teams to improve design quality and implementation efficiency.
Excellent communication and cross-functional collaboration skills.
Nice to have
Experience with industry-standard EDA tools for synthesis and physical design.
Strong understanding of timing, congestion, power, and area optimization techniques.
Experience with high-performance CPU, GPU, AI/ML, or networking SoCs.
Culture & Benefits
Long-term onsite contract in Sunnyvale, California.
Collaboration with a high-performing silicon engineering team across the chip development lifecycle.
Contract engagement; expected rate and C2C/1099 details are requested during application.
Hiring process
Submit an updated resume with current location, visa status, availability, relocation preference, and expected all-inclusive C2C/1099 rate.
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