Sr. Engineer, Process Development (InP Photonics)

Location: Rowland, CA / City of Industry, CA; onsite in a III-V cleanroom environment.

Salary: $95,000–$135,000 per year.

Company

hirify.global develops semiconductor and photonic technologies, including InP photonic devices and wafer-fabrication processes.

What you will do

• Own photolithography, PECVD, dry etch, wet etch, and/or metallization modules for InP buried-heterostructure DFB lasers and gain-chip production.
• Develop and optimize lithography, dielectric deposition, Mesa etch, surface preparation for MOCVD regrowth, and ohmic-contact processes.
• Define process windows, specifications, SPC strategies, and control limits using designed experiments and statistical analysis.
• Investigate process excursions, yield loss, and drift; identify root causes and implement corrective actions with Equipment Engineering.
• Manage process documentation, change control, qualifications, and transitions of new or modified processes into volume production.
• Collaborate with Device, MOCVD/Epitaxy, Test, Quality, Production Planning, technicians, and supervisors; prepare technical reports and support audits and failure analysis.

Requirements

• Master’s degree in materials science, electrical engineering, chemical engineering, physics, or a related engineering or science field.
• 2–5 years of semiconductor or photonics wafer-processing experience; relevant graduate research in III-V device fabrication may count toward experience. Direct III-V/InP process experience is preferred.
• Hands-on experience in one or more of photolithography, PECVD, dry etch, wet etch, and metallization.
• Strong knowledge of semiconductor process physics and chemistry, including lithography, thin-film deposition, plasma and wet etch, and III-V metallization/ohmic-contact formation.
• Proficiency in statistical analysis, SPC, and DOE using JMP, Minitab, Python, or equivalent.
• Ability to independently lead root-cause investigations, drive corrective actions to closure, and correlate process data with device electrical and optical performance.
• Familiarity with CD-SEM, profilometry, ellipsometry, XRD, SEM, and TLM test structures.
• Strong written and verbal communication skills and the ability to present technical results to management and cross-functional teams.
• Ability to work with technicians, supervisors, and engineers; work in a cleanroom for extended periods across multiple process bays; and safely handle acids, solvents, process gases, and precious metals.
• May need flexibility to support engineering runs or excursions outside standard shift hours.

Nice to have

• Experience with InP-based laser or photonic integrated-circuit fabrication.

Culture & Benefits

• Onsite work in a III-V cleanroom with cross-functional collaboration and minimal supervision.
• Work includes interaction with Wafer Fab Supervisors, Technicians, Equipment Engineering, Device and Test Engineering, and Quality.
• Base salary is estimated at $95,000–$135,000 annually and depends on qualifications, skills, education, experience, location, and other compensation elements.