Chip Architect (AI)

Location: Palo Alto, California, United States; onsite.

Salary: $250,000–$400,000 per year.

Company

Early-stage, venture-backed AI semiconductor startup developing a specialized accelerator and software stack for large language model inference.

What you will do

• Translate inference system requirements into detailed chip- and block-level microarchitecture specifications.
• Develop architecture across compute, memory hierarchy, interconnects, and data movement.
• Evaluate throughput, latency, power, performance, and area trade-offs using quantitative analysis.
• Collaborate with RTL, design verification, and physical design engineers to translate architecture into efficient hardware and resolve implementation constraints.
• Analyze workload characteristics, hardware utilization, and performance bottlenecks to improve inference efficiency.
• Support first-generation silicon development, design integration, implementation trade-offs, tapeout readiness, and future accelerator architecture.

Requirements

• Extensive experience in ASIC/SoC architecture or microarchitecture, with ownership of significant hardware design decisions.
• Strong understanding of digital hardware architecture and complex semiconductor implementation challenges.
• Deep expertise in compute architectures, memory hierarchies, interconnects, and data movement.
• Ability to translate architectural concepts into detailed, implementable microarchitecture.
• Experience evaluating throughput, latency, power, performance, and area trade-offs.
• Understanding of how architectural decisions affect RTL implementation, verification, and physical design.
• Ability to analyze complex hardware performance bottlenecks and develop quantitative, evidence-based solutions.
• Experience collaborating with RTL, verification, and physical design engineering teams.
• Staff-to-Principal-level technical depth and willingness to remain hands-on in architecture development and engineering problem-solving.

Nice to have

• Experience architecting AI accelerators, inference ASICs, GPUs, or other high-performance compute processors.
• Familiarity with LLM inference workloads and specialized machine learning accelerator architectures.
• Experience with performance modeling, workload characterization, and architecture exploration.
• Knowledge of memory bandwidth optimization, compute utilization, and efficient data movement.
• Experience taking semiconductor architectures through RTL implementation, physical closure, and tapeout.
• Involvement in successful ASIC/SoC tapeouts and post-silicon performance analysis.
• Experience developing first-generation silicon or working at an early-stage semiconductor startup.

Culture & Benefits

• Hands-on ownership of microarchitectural decisions and hardware implementation strategy.
• Direct collaboration across architecture, RTL, verification, and physical design.
• Technical involvement in first-generation silicon and future chip architectures.
• Medical, dental, and vision insurance, plus a 401(k).

Hiring process

• Two to three conversations focused on previous technical projects, chip architecture experience, and engineering problem-solving.
• References may be requested.
• Further company, technology, and roadmap details are shared under NDA as the process progresses.