Senior ASIC Design Engineering Manager

Location: Remote for employees residing within the United States; department location is Austin, Texas.

Company

hirify.global develops scale-out networking solutions for AI and high-performance computing datacenters, integrating hardware, software, and system-level technologies.

What you will do

• Lead and grow the RTL design engineering team and manage full-lifecycle development of high-performance networking ASICs.
• Own RTL delivery schedules across SoC subsystems, full-chip milestones, tape-out readiness, and committed project plans.
• Track schedule risks, use data-driven insights, and reallocate resources to keep projects on track.
• Coordinate RTL delivery with Design Verification and emulation enablement, including feedback loops and dependencies.
• Facilitate physical design handoffs, track timing-closure feedback, and support physical design signoff and tape-out milestones.
• Own headcount planning, organizational design, hiring, skill-gap analysis, and talent acquisition strategy for the ASIC department.

Requirements

• 15+ years of semiconductor industry experience, preferably in high-performance designs on advanced technology nodes, including at least 5 years of people management.
• B.S. or M.S. in Computer Engineering, Electrical Engineering, or a related technical field, or equivalent practical experience.
• Deep understanding of collaboration between Design, Verification, Emulation, and Physical Design teams.
• Experience leading large engineering organizations through multiple full-cycle ASIC product launches in a remote environment.
• Ability to coordinate multiple projects, manage risks and escalations, and work under tight schedules and budget constraints.
• Strong technical expertise in microarchitecture development, RTL coding with Verilog and SystemVerilog, synthesis, STA/timing closure, physical design, and verification methodologies.
• Exposure to industry standards or protocol stacks such as PCIe, Ethernet, UCIe, or UALink.
• Demonstrated ability to optimize designs for PPA and integrate major subsystems including interconnect, I/O, and memory.

Nice to have

• Exposure to AI-based design implementation and verification flows, scripting for automation, milestone tracking, and flow integration.
• Experience building globally distributed ASIC design teams and scaling engineering practices in a remote environment.

Culture & Benefits

• Flexible remote work environment with collaboration across a global organization spanning six countries and multiple U.S. states.
• Competitive compensation package with equity, cash, and incentives.
• Medical, dental, vision, disability, life, dependent care, accidental injury, and pet insurance.
• Paid holidays, sick time, bonding leave, pregnancy disability leave, and Open Time Off for regular full-time exempt employees.
• 401(k) with company match and performance-based incentives, including an annual bonus depending on the role.