Lead RTL Design Engineer (ASIC)

Location: Hybrid in Mountain View, United States.

Company

hirify.global is an applied AI company developing foundational hardware and software for the semiconductor industry, AI infrastructure, and broader computing systems.

What you will do

• Lead and own RTL development from microarchitecture specifications through tapeout, including synthesizable SystemVerilog for datapath logic, control, and memory interfaces.
• Set RTL coding standards, refine design methodology, organize the RTL design team, track progress, and support hiring.
• Translate high-level architectural specifications into implementable microarchitectures and contribute to architecture and design reviews.
• Partner with verification engineers on verification plans, debugging, conventional and formal testing, and coverage closure.
• Collaborate with physical design on timing closure, PPA optimization, floorplanning constraints, and DFT.
• Prepare tapeout criteria, sign off on tapeout readiness, and support post-silicon bring-up as needed.

Requirements

• Experience leading an RTL design team through multiple block and top-level tapeouts.
• Hands-on experience writing production RTL in SystemVerilog and closing multiple blocks and designs through synthesis and place-and-route.
• Experience with datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront.
• Strong debugging skills across simulation, waveforms, and formal counterexamples.
• Ability to work directly with architects and physical designers.
• Ability to lead initiatives, energize the RTL team, and foster cross-functional alignment across architecture, verification, and physical design.

Nice to have

• Experience at an AI chip company where design and verification were tightly coupled.
• Experience with interface architectures such as PCIe, Ethernet, and memory devices.
• Familiarity with FPGAs.
• Experience using AI-assisted RTL or EDA tooling in the design workflow.
• Exposure to physical design constraints, floorplanning, or timing-driven RTL development.

Culture & Benefits

• Collaborative, execution-focused environment with high standards for RTL design.
• Cross-functional work across architecture, RTL, verification, and physical design.
• Work on novel computing architectures where hardware and algorithms are developed together.
• Inclusive workplace and equal employment opportunity commitment.
• Reasonable accessibility accommodations are available.