Platform Signal/Power Integrity Engineer Lead

Location: On-site in Penang, Malaysia.

Company

hirify.global is hiring for a platform hardware engineering role supporting Intel next-generation validation and product platforms.

What you will do

• Lead Signal Integrity and Power Integrity activities for complex platform, board, and package designs.
• Perform pre-layout and post-layout SI/PI simulations, analyze channel loss, reflection, crosstalk, jitter, timing margin, power delivery networks, power noise, and voltage droop.
• Drive platform electrical architecture, schematic reviews, PCB layout reviews, routing constraints, electrical budgets, design margins, and sign-off recommendations.
• Define stack-up, impedance, return path, power distribution, termination, decoupling, and high-speed interface routing requirements.
• Correlate simulations with laboratory measurements, perform electrical characterization, and debug signal integrity, timing, and power delivery failures during board bring-up and validation.
• Lead root-cause analysis, compliance testing, design guideline development, cross-functional SI/PI reviews, mentoring, and continuous improvement initiatives.

Requirements

• Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• 9+ years of experience in Signal Integrity, Power Integrity, Platform Hardware Design, or Board Design.
• Strong understanding of high-speed digital design, power delivery architectures, SI/PI fundamentals, transmission line theory, channel modeling, termination techniques, and power distribution network analysis.
• Experience with high-speed PCB design and implementation, schematic review, and board-level electrical analysis.
• Experience analyzing crosstalk, reflection, jitter, eye diagrams, S-parameters, power noise, and voltage droop.
• Proven debugging and root-cause analysis skills, with excellent communication and cross-functional collaboration skills.
• Experience with one or more high-speed interfaces: DDR4/DDR5, LPDDR4/LPDDR5, PCIe Gen4/Gen5/Gen6, USB4/Thunderbolt, Ethernet, SATA, CXL, UCIe, or high-speed SerDes.

Nice to have

• Experience with Cadence Sigrity, Cadence Allegro, Ansys HFSS, Ansys SIwave, ADS, SPICE-based simulation tools, or power-aware SI/PI simulation tools.
• Experience reviewing and signing off schematics, PCB layouts, routing constraints, and SI/PI compliance requirements.
• Experience defining routing guidelines and electrical design rules for high-speed interfaces.
• Familiarity with package-board co-design methodologies.
• Knowledge of DFM, DFT, and reliability considerations.

Culture & Benefits

• On-site work model in Penang, Malaysia.
• Shift 1 schedule in Malaysia.
• Cross-functional collaboration across platform, silicon, package, PCB layout, firmware, validation, and manufacturing organizations.
• Employment opportunity for an experienced hire.