Назад
Company hidden
2 дня назад

Principal Engineer - Ecosystem IP Quality (Semiconductor IP)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Malaysia
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Principal Engineer - Ecosystem IP Quality (Semiconductor IP): Qualifying and validating semiconductor IP libraries across technology platforms, with an accent on incoming IP QA, regression testing, PDK compatibility, and customer tape-out support. Focus on physical verification, DRC/LVS/DFM, PEX extraction, SPICE simulation, PHY co-simulation, and improving IP qualification automation.

Location: Penang, Malaysia

Company

hirify.global is a semiconductor manufacturer producing power-efficient and high-performance solutions for high-growth markets, with manufacturing operations across the United States, Europe, and Asia.

What you will do

  • Perform incoming IP quality assurance against predefined checklists, verify IP design kits and silicon deliverables against contracts, and issue approval or non-conformance certificates.
  • Qualify IP merge kits for customer tape-out and maintain IP information in the IP database and catalog.
  • Define test cases, execute IP regression testing, and assess the impact of PDK updates on IP.
  • Perform physical verification including DRC, LVS, DFM, PEX extraction, and SPICE simulation against defined criteria.
  • Review assessment results with internal and external stakeholders, drive technical issues to closure, and support customer IP queries.
  • Maintain regression databases, SOPs, audit documentation, technical issue records, waiver documents, and assessment reports; support scripting and automation.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or an equivalent field.
  • Minimum 10 years of experience in the IC design field.
  • Proficiency in SystemVerilog/Verilog and experience with simulation verification.
  • Knowledge of verification methodology development for complex circuits.
  • Knowledge of DFT, scan insertion, ATPG, and functional test vectors.
  • Hands-on experience with industry-standard CAD tools.
  • Experience with PHY co-simulation using RTL and SPICE, including Verilog testbench development and debugging in the Cadence co-simulation environment.
  • Knowledge of the digital portion of PHYs using standard CMOS ASIC flow and digital circuit design for PHY protocols.
  • Knowledge of Tetramax models and ATPG coverage.
  • Knowledge of IC process and layout design.
  • Compliance with applicable environmental, health, safety, and security policies and procedures.

Nice to have

  • Knowledge of RF design.
  • Knowledge of physical verification, including DRC, LVS, and DFM.
  • Knowledge of scripting and automation languages.

Culture & Benefits

  • Multicultural and inclusive workplace focused on respect, diversity, innovation, and collaboration.
  • Employment is subject to applicable background checks, medical screenings, and local laws.
  • No recruitment fees are charged at any stage of the hiring process.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →