Senior Analog and Mixed Signal Design Engineer (SerDes)

Location: On-site in Hillsboro, Oregon, United States, with an additional hirify.global location in Santa Clara, California, United States.

Annual salary: $141,910–$269,100 USD.

Company

hirify.global develops semiconductor technologies, including advanced analog, mixed-signal, high-speed I/O, and process technology solutions.

What you will do

• Define SerDes link architectures for 224G/448G-class PAM4 electrical links, PCIe Gen7/Gen8, and UCIe, including channel analysis, link budgets, jitter and noise budgets, and equalization partitioning.
• Build and maintain statistical and time-domain link models in MATLAB or Python using COM and IBIS-AMI, and derive specifications for TX, RX, ADC, and clocking circuits.
• Lead transistor-level design of SerDes TX drivers, RX analog front ends, DFE and slicers, time-interleaved ADC front ends, CDRs, phase interpolators, PLLs, and clock distribution.
• Drive test-chip definition, integration, tapeout readiness, silicon bring-up, and correlation of BER, eye, jitter, and power measurements with models.
• Translate SerDes requirements into process and PDK requirements and lead design-technology co-optimization with process, PDK, and template-library teams.
• Mentor engineers, lead design reviews, and represent hirify.global Foundry in technical engagements with IP partners and foundry customers.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering plus 6+ years of industry experience in high-speed wireline SerDes circuit design; or a master’s degree plus 4+ years; or a Ph.D. plus 2+ years.
• Transistor-level design experience with SerDes TX, RX, or clocking circuits in at least one silicon-proven design operating at 28 Gb/s per lane or higher.
• Experience in at least one of the following: SerDes link architecture, including channel and link-budget analysis or equalization trade-off studies; laboratory validation of high-speed links, including BER, eye, or jitter measurement and simulation correlation; or behavioral/statistical link modeling in MATLAB or Python.

Nice to have

• Silicon-proven designs at 56 Gb/s PAM4 or higher in FinFET or GAA CMOS, with multiple tape-outs and block ownership.
• Experience across architecture, laboratory validation, and link modeling.
• Experience with ADC/DSP-based receivers at 112 Gb/s PAM4 or higher, including time-interleaved ADC design; 224 Gb/s-class link development; PCIe Gen6/Gen7 PHY; or UCIe die-to-die PHY development.
• Design experience on 5nm-class or more advanced nodes and design-technology co-optimization with process teams.
• Package and channel co-design experience, including package/PCB channel modeling, signal and power integrity, and crosstalk.
• First-author publications at ISSCC, VLSI Symposium, CICC, or JSSC, or patents in SerDes circuits or architecture.
• Technical leadership of a multi-engineer SerDes design team through full PHY delivery.

Culture & Benefits

• On-site work model with Shift 1 schedule in the United States.
• Competitive compensation with stock bonuses.
• Health, retirement, and vacation benefits.
• Employment at hirify.global Foundry with opportunities for technical leadership and collaboration across design, process, PDK, layout, and measurement teams.