Principal Systems/DSP Engineer (SerDes)

Location: Bay Area, United States; Workplace: On-site

Company

hirify.global is a chiplet startup developing high-performance, manufacturable interconnect and SerDes IP for next-generation chiplet-based systems.

What you will do

• Define low-power DSP architectures for 224G PAM4 and 448G SerDes designs, balancing power, performance, and area.
• Build behavioral models of mixed-signal transceiver circuits using MATLAB, Simulink, C, and/or Python.
• Develop and optimize equalization, adaptive channel-compensation, CDR, and FEC algorithms.
• Derive AFE, DAC/ADC, and PLL performance targets from BER and link-budget analyses.
• Collaborate with analog, digital RTL, verification, and physical design teams on silicon-ready implementations.
• Lead silicon bring-up, lab validation, characterization, interoperability, and standards-compliance testing.

Requirements

• Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of DSP system architecture and algorithm-development experience in high-speed serial communications, including hands-on work at 112G PAM4 or higher.
• Expertise in digital communications, signal processing, PAM4, equalization, CDR loop dynamics, and statistical channel modeling.
• Expert-level proficiency in MATLAB, Simulink, C, and/or Python for production-quality behavioral modeling.
• Experience with 112G/224G SerDes products, tapeout or silicon characterization, and relevant Ethernet, PCIe, UCIe, and OIF CEI standards.
• Ability to work on-site in the Bay Area.

Nice to have

• Experience with chiplet die-to-die interconnects, optical/electrical interfaces such as VCSEL or EML, or DRAM/HBM PHY systems.

Culture & Benefits

• Work with a cross-functional team of experts operating from first principles.
• Participate in developing high-volume, high-performance, manufacturable products.
• Fun work environment with excellent benefits.