Principal Systems/DSP Engineer (SerDes)

Location: Bay Area, United States; on-site

Company

hirify.global is a chiplet startup developing high-performance, manufacturable chiplet-based systems and SerDes IP.

What you will do

• Define low-power DSP architectures for 224G PAM4 and 448G SerDes, balancing power, performance, and area.
• Build behavioral models of mixed-signal transceivers using MATLAB, Simulink, C, and/or Python for system-level prediction and design specification.
• Develop and optimize FFE, DFE, CTLE, MLSE/MLSD, adaptive channel-compensation, and CDR algorithms, including convergence, calibration, jitter tolerance, and frequency acquisition strategies.
• Derive AFE, DAC/ADC, and PLL targets from BER and link-budget analysis; perform system simulations and power/performance trade-off studies.
• Develop FEC solutions, including inner/outer FEC, RS-FEC KP4/KP8, and concatenated coding for IEEE 802.3dj and OIF CEI-224G.
• Collaborate with analog, digital RTL, physical design, verification, characterization, customers, and partners on silicon implementation, bring-up, interoperability, benchmarking, debugging, and standards compliance.

Requirements

• Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of DSP system architecture and algorithm-development experience for high-speed serial communications, including hands-on work at 112G PAM4 or higher.
• Deep knowledge of digital communications and signal processing, including PAM4, equalization architectures, CDR loop dynamics, and statistical channel modeling.
• Expert-level MATLAB, Simulink, C, and/or Python skills, with experience building production-quality behavioral models.
• Strong knowledge of Ethernet IEEE 802.3ck/df/dj, PCIe, UCIe, and OIF CEI specifications.
• Understanding of DAC/ADC architectures, PLL phase noise, AFE linearity, and their effects on DSP performance and link budgets.
• Experience translating algorithmic intent into silicon-ready implementations across analog, digital, and verification teams.
• Hands-on experience with 112G/224G SerDes products and proven tapeout or silicon-characterization results.
• Detailed knowledge of OIF CEI-224G and IEEE 802.3dj, including link-budget allocation, compliance testing, and FEC performance metrics.

Nice to have

• Experience with chiplet die-to-die interconnects, optical/electrical interfaces such as VCSEL and EML, or DRAM/HBM PHY systems.

Culture & Benefits

• On-site work in the Bay Area within the Engineering department.
• Cross-functional collaboration with experts in analog, digital RTL, physical design, verification, and characterization.
• Fun work environment with excellent benefits.