Design Implementation Engineer (ASIC/SoC)

Location: San Jose, California, United States; other listed locations include Allentown, Pennsylvania, Fort Collins, Colorado, and Broomfield, Colorado. Onsite role.

Annual base salary: USD 121,900–195,000. Additional discretionary annual bonus and equity awards may be available.

Company

hirify.global develops semiconductor and technology solutions and applies established design methodologies and milestone flows to deliver right-first-time silicon.

What you will do

• Execute block- and SoC-level design implementation activities across floor-planning, partitioning, placement, clock tree synthesis, routing, timing analysis, timing closure, and physical verification.
• Drive tools and methodologies to achieve target power, performance, and area metrics.
• Perform equivalence checks, static timing analysis, timing closure, and power optimization.
• Implement timing and functional engineering change orders.
• Apply hirify.global's design methodology and milestone flow to support right-first-time silicon.

Requirements

• BS in Electrical Engineering, Computer Engineering, or a related field with 8+ years of related experience, or MS in the same fields with 6+ years of related experience.
• Extensive proficiency in design implementation activities at both block and SoC level.
• Hands-on experience with timing analysis and place-and-route tools for ASIC/SoC design.
• Experience with floor-planning, partitioning, placement, clock tree synthesis, routing, physical verification, constraints development and validation, timing analysis, and timing closure.
• Experience with formal verification, timing analysis, and ECO implementation.
• Experience working on the tapeout of at least 1–2 ASICs in 7nm or smaller technologies.
• Ability to solve problems, work independently, learn and adapt to new tools and methodologies, and communicate effectively.
• Experience working in a global team and dynamic environment.

Nice to have

• Experience with PrimeTime, ICC2, Innovus, Calibre, LEC, and related implementation or verification tools.
• Full-chip tapeout experience using 7nm and smaller technologies.
• Primary expertise in place and route or timing, including constraints and static timing analysis.

Culture & Benefits

• Medical, dental, and vision plans.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Employee Assistance Program, paid holidays, paid sick leave, and vacation time.
• Paid family leave and other leave benefits in accordance with applicable laws.
• Potential discretionary annual bonus, competitive new-hire equity grant, and annual equity awards.