Senior Staff Advanced Packaging Design Engineer (AI)

Location: Burlington, VT, United States; other listed locations include Westborough, MA and Chandler, AZ. The role involves collaboration across multiple global time zones.

Expected base pay: $142,700–$211,230 per annum. The role is also eligible for bonus and equity plans.

Company

hirify.global develops semiconductor solutions and packaging technologies for enterprise, cloud, AI, carrier, high-performance computing, and networking infrastructure.

What you will do

• Lead small teams of design and simulation engineers in delivering advanced packaging solutions.
• Drive package definition and architecture development for performance-line products.
• Interface with package suppliers to select technologies and ensure manufacturability, performance, reliability, and cost targets.
• Develop multi-chip and multi-component package solutions, including 2.5D and 3D packages, co-packaged copper or optical solutions, and advanced substrates.
• Manage cross-functional programs involving internal stakeholders, external partners, and customers.
• Collaborate with chip design and electrical simulation teams to optimize package and system designs.

Requirements

• Extensive experience in substrate and/or board design for advanced packaging technologies.
• Strong understanding of design-for-manufacturing, reliability principles, electrical performance, and trade-off decisions.
• Proven ability to lead complex package architecture development projects involving internal stakeholders, external partners, and customers.
• Expertise with Cadence 3DIC, ISP, APD, and SiP tools and workflows.
• Bachelor’s degree in Electrical Engineering or a related field with 5+ years of relevant professional experience, or a Master’s degree or Ph.D. with 3+ years of relevant professional experience.
• Understanding of design rules, breakout, placement and routing, signal shielding, reference planes, power distribution, and pinout development.
• Experience with HBM, DDR, SerDes, D2D, D2H, ADC, DAC, PCIe, Ethernet, and related technologies.
• Strong understanding of signal and power integrity across substrate, board, package, and system levels.
• Understanding of advanced 2.5D and 3D packaging technologies, including CoWoS-S/R/L, EMIB, CPO, and CPC.
• Ability to manage cross-functional programs, communicate and present effectively, document work, and collaborate with stakeholders across global time zones.

Nice to have

• Familiarity with Cadence Sigrity, Clarity, Innovus, Virtuoso, Ansys, AutoCAD, and SolidWorks.
• Experience contributing to tool, process, and workflow development and library maintenance.
• Familiarity with running and interpreting signal and power integrity simulations.
• Strong interpersonal skills and willingness to learn.

Culture & Benefits

• Employee stock purchase plan with a two-year look-back period.
• Bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
• Family support programs and mental and physical health resources.
• Recognition and service awards.
• Reasonable accommodation is available during the selection process.
• Applicants may undergo export license review before employment; access to export-controlled technology requires eligibility under applicable U.S. regulations.

Hiring process

• Interviews evaluate individual experience, thought process, and communication skills in real time.
• AI tools, transcription apps, automated answer generators, and automated note-taking bots are not permitted during interviews.