signal integritypower integritypackage designcustomer facing communicationadvanced packagingsemiconductor packagingchiplets3d ic
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
$162к-302к/год
$120к$160кмедиана$200к
По похожим ролям (48) ~ $160к/год
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Сильная вакансия
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Чёткая senior-позиция в ведущей компании по разработке решений для полупроводниковой отрасли, с фокусом на передовую упаковку и новые архитектуры чипов; главный нюанс - требуется более 10 лет узкоспециализированного опыта.
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Высокий порог входаПонятные задачиПередовые технологии
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Solutions Architect Engineer (AE) (Advanced Packaging): Deploying and optimizing Cadence 3D-IC design flows for advanced packaging, chiplet architectures, AI/HPC packages, and heterogeneous integration with an accent on customer solutions, design-signoff methodologies, and technical pre-sales. Focus on developing packaging workflows, supporting proof-of-concepts and production deployments, and solving complex SI/PI, thermal, connectivity, and manufacturing challenges.
Location: United States; remote or hybrid. Approximately 2%–5% travel depending on customer demand and business needs.
Annual salary range for California: $162,400–$301,600, plus potential incentive compensation, bonus, equity, and benefits.
Company
hirify.global develops technology solutions for the semiconductor and electronic design industries.
What you will do
Provide technical leadership and application support for hirify.global 3D-IC and advanced packaging design solutions.
Help semiconductor companies, OSATs, foundries, and system companies develop package architectures, design implementations, methodologies, and production deployments.
Develop and demonstrate workflows for organic substrates, silicon interposers, wafer-level packaging, 2.5D and 3D-IC integration, and chiplet-based architectures.
Support customer evaluations, proof-of-concepts, benchmarks, technical presentations, demonstrations, workshops, and training.
Collaborate with sales on technical pre-sales activities and with R&D on customer requirements, enhancement requests, and future technology needs.
Develop best practices, application notes, reference flows, customer-success methodologies, and product direction for advanced packaging.
Requirements
Bachelor’s degree in Electrical or Electronics Engineering or a related discipline; a Master’s degree is preferred.
10+ years of experience in semiconductor packaging, IC packaging, PCB, substrate, or interposer design.
Strong knowledge of advanced package design methodologies, 2.5D and 3D-IC integration, chiplet-based architectures, package manufacturing and assembly, high-speed signal design, and power delivery networks.
Experience with package layout, routing, constraint management, and package signoff.
Understanding of package stackups, bump planning, escape routing, and substrate technologies.
Experience with design-signoff methodologies including DRC/LVS, connectivity verification, electrical rule checking, thermal analysis, signal integrity, and power integrity.
Excellent customer-facing communication and presentation skills.
Ability to work independently while collaborating across global teams.
Nice to have
Experience with hirify.global Integrity 3D-IC Platform, hirify.global Sigrity, Clarity 3D Solver, or hirify.global Allegro X APD.
Knowledge of UCIe, HBM, AI accelerator packaging, and heterogeneous integration.
Experience supporting foundry and OSAT design flows.
Understanding of semiconductor assembly, reliability, and manufacturing processes.
Culture & Benefits
Work focused on solving complex technology challenges and developing semiconductor design solutions.
Remote or hybrid work arrangement in the United States.
Paid vacation and paid holidays.
401(k) plan with employer match, employee stock purchase plan, and medical, dental, and vision plan options.
Potential bonus, equity, and other incentive compensation; sales positions generally include an OTE structure.
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