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3 дня назад

ASIC Package Design Engineer (AI)

143 800 - 230 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
ASIC Package Design Engineer (AI) (Flip-Chip BGA/SerDes): Designing high-performance flip-chip BGA packages for ASICs used in AI, networking, HPC, and 5G systems with an accent on signal integrity, power integrity, manufacturability, reliability, and thermal performance. Focus on developing critical package structures for 448G-and-higher SerDes, ADC/DAC, DDR, and HBM, while improving design automation and coordinating multiple projects.

Location: On-site at the hirify.global office in San Jose, California, United States, five days per week; other listed locations include Austin, Texas, and Fort Collins, Colorado. This is not a remote-work position.

Annual base salary: USD 143,800–230,000. Additional discretionary annual bonus and equity awards may be available.

Company

hirify.global develops high-performance ASIC package designs for artificial intelligence, networking, high-performance computing, and 5G base stations.

What you will do

  • Take overall design responsibility for ASIC packages, including signal integrity, power integrity, manufacturability, reliability, and thermal considerations.
  • Design critical package structures for high-speed SerDes, ADC/DAC, DDR, HBM, and other ASIC interfaces.
  • Perform physical package design and layout for flip-chip BGA packages.
  • Schedule, prioritize, and track work across two or more projects simultaneously.
  • Manage projects and interface with customers while collaborating with internal engineers and external vendor designers.
  • Improve design-team efficiency through process development, automation, and documentation.

Requirements

  • BSEE or a similar degree with 12+ years of experience in flip-chip BGA package design, including high-speed SerDes, or an MSEE or similar degree with 10+ years of work experience.
  • Knowledge of package-level signal integrity and power integrity and their application to package designs.
  • Self-management and organization skills.
  • Ability to cooperate with a worldwide team across multiple time zones, including co-design with internal team members and external vendor designers.
  • Ability to work on-site at the hirify.global office five days per week.

Nice to have

  • Cadence APD (Allegro Package Designer) experience; an equivalent tool is acceptable.
  • One or more years of experience with Cadence SKILL for Allegro or similar design-automation coding experience and interest.

Culture & Benefits

  • Collaboration with a worldwide R&D team working across multiple time zones.
  • Medical, dental, and vision plans.
  • 401(k) participation with company matching and an Employee Stock Purchase Program.
  • Company-paid holidays, paid sick leave, vacation time, and applicable paid family and other leaves of absence.
  • Employee Assistance Program and potential annual bonus and equity awards.

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