Principal / Senior Principal Electrical Design Engineer (High-Speed Hardware)

Location: San Jose, California, United States

Base pay range: $185,000–$240,000 per year

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, UALink, and the COSMOS software suite.

What you will do

• Define board-level hardware architecture, technical roadmaps, design standards, and methodologies across multiple product lines and platform generations.
• Architect and own complex multi-layer PCBs for chassis boards, NIC cards, PCIe add-in cards, and high-performance connectivity platforms.
• Drive signal integrity, power delivery, stack-up, impedance, sequencing, protection, control-interface, and observability strategies.
• Lead hardware bring-up, validation, root-cause analysis, debug, corrective actions, and improvements to validation and failure-analysis processes.
• Partner with silicon, SI/PI, mechanical, thermal, firmware, software, systems, manufacturing, suppliers, and ASIC teams throughout the product lifecycle.
• Mentor senior and lead engineers, lead technical and architectural reviews, and represent the hardware organization in executive, customer, and industry engagements.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering or a closely related field; an advanced degree is preferred.
• 12+ years of progressive hardware design experience with deep board-level electrical engineering expertise and technical leadership across multiple product generations.
• Production hardware architecture and delivery experience for server, networking, storage, or high-performance compute systems at scale.
• Expert experience with high-speed SerDes systems using Ethernet, PCIe, or related protocols, including hands-on PCIe Gen5/Gen6 and 400G/800G Ethernet system design.
• Expert signal integrity knowledge covering impedance control, differential-pair routing, channel-loss optimization, crosstalk mitigation, and high-speed interface layout review.
• Expert power integrity and PDN design knowledge, including sequencing, decoupling, transient response optimization, and system-level power architecture tradeoffs.
• Mastery of industry-standard schematic capture and PCB design/review tools such as Cadence Allegro or OrCAD.
• Experience leading complex hardware bring-up and debug using oscilloscopes, protocol analyzers, and advanced lab instrumentation.
• Ability to lead cross-functional teams, influence technical direction across organizational boundaries, and mentor engineers.

Nice to have

• Architecture experience for NIC cards, accelerator cards, or other PCIe add-in card platforms across multiple generations.
• Experience leading server chassis or system board programs in dense, thermally constrained, high-availability environments.
• Expertise with 800G Ethernet, emerging 1.6T electrical interfaces, retimers, redrivers, advanced clocking, and high-speed interconnect subsystems.
• Experience with PCIe and Ethernet compliance and validation workflows, including contributions to industry specifications or standards bodies.
• Experience managing contract manufacturers, production ramps, and yield optimization for complex hardware products.
• Scripting and automation proficiency in Python or similar languages for lab automation, measurement analysis, hardware characterization, and design-flow optimization.
• Experience influencing product strategy and roadmap decisions at the organizational level.

Culture & Benefits

• Base pay is determined by location, experience, and compensation for similar positions.
• Applications are encouraged from candidates with diverse backgrounds and experiences, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.