Principal Physical Verification Engineer (ASIC)

Location: San Jose, California, USA. Must work in person at the San Jose site; no remote work is allowed.

Annual base salary: USD 143,800–230,000, plus a discretionary annual bonus and potential equity awards.

Company

hirify.global’s ASIC Products Division develops custom high-performance silicon solutions for hyperscale cloud providers, AI companies, and networking infrastructure leaders.

What you will do

• Execute chip-level physical verification and resolve related issues.
• Set up DRM runsets for advanced nodes and verification tool flows.
• Manage rules for top-level floorplanning, I/O planning, and bump planning.
• Resolve physical design issues related to chip integration and assembly.
• Provide technical direction for DRC, LVS, ERC, and PERC verification methodologies.
• Develop physical verification best practices and runtime optimizations.

Requirements

• Bachelor’s degree in Electrical Engineering or Electronics Engineering.
• 12+ years of relevant experience.
• Hands-on experience running physical verification using LVS, DRC, ERC, and PERC.
• Experience with EDA tools and flows such as ICV, Calibre, and Pegasus.
• Rule-deck coding experience in ICV, Calibre, or Pegasus.
• Experience resolving chip-level DRC, LVS, and EMIR issues for advanced nodes, including silicon tapeout experience.
• Experience analyzing ESD, latch-up, floating-gate, and power-domain isolation vulnerabilities through ERC/PERC.
• Experience managing automated dummy metal, poly, and diffusion filling to meet local and global density rules.
• Experience implementing DFM fixes, including critical-area analysis, via doubling, and edge-displacement rules.
• Experience collaborating with physical design and place-and-route teams to resolve top-level integration bottlenecks.
• Excellent verbal and written communication skills.
• Must work in person at the San Jose site; remote work is not allowed.

Nice to have

• Experience with scripting languages such as Python, Tcl, or Perl.

Culture & Benefits

• Work within a physical design team developing advanced 3nm and 2nm silicon and 2.5D/3D chiplet solutions.
• Medical, dental, and vision plans.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Employee Assistance Program, company-paid holidays, paid sick leave, vacation, and applicable paid family and other leaves.
• Discretionary annual bonus and potential new-hire and annual equity awards, subject to plan documents.