Design Verification Engineer

Location: Hybrid, with time split between the assigned hirify.global site in Santa Clara, California or Austin, Texas, and off-site work. United States work locations.

Annual salary: $141,910–$200,340 USD.

Company

hirify.global develops semiconductor technologies and next-generation interconnect and chassis IPs across multiple product families.

What you will do

• Develop and execute verification plans and testbenches for interconnect and chassis IP features at the IP and subsystem levels.
• Build reusable verification components, checkers, constrained-random tests, and debug infrastructure to improve coverage and productivity.
• Collaborate with architecture, design, and software teams on specification reviews, feature clarification, bug triage, and closure.
• Analyze simulation failures, identify root causes, and drive fixes to closure with clear technical communication.
• Contribute to functional coverage planning, coverage closure, quality signoff, simulation, and formal verification under the guidance of technical leads.
• Improve verification automation, regression quality, and development efficiency using AI-assisted workflows.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Science, or a related field with 5+ years of industry experience, or a Master's degree with 4+ years of relevant experience.
• Programming fundamentals, algorithmic problem-solving skills, and demonstrated hands-on coding experience in SystemVerilog, C/C++, and Python.
• Foundation in simulation-based verification methodologies, including UVM/ABV, with exposure to formal verification concepts, testbench development, debugging, and coverage-driven verification.
• Hands-on experience using AI-assisted development tools daily for coding, debugging, and test development.
• Exposure to interconnects and bus protocols such as AMBA AXI/ACE/CHI, PCIe, CXL, or UCIe.
• Ability to write clean, reusable, and maintainable verification code and automation scripts.
• Ability to collaborate effectively across architecture, design, and software teams.

Nice to have

• Understanding of cache coherency and memory consistency models.
• Experience with external interfaces and system integration debugging.
• Experience with formal verification tools such as JasperGold, VC Formal, or similar, and with emulation or FPGA-based verification.
• Exposure to RTL concepts, physical design, or CAD tool flows.
• Prior work with system IPs such as MMUs, SMMUs, IOMMUs, and interrupt controllers.

Culture & Benefits

• Hybrid work model combining on-site work at an assigned hirify.global site with off-site work.
• Competitive pay, stock bonuses, health benefits, retirement benefits, and vacation.
• Daily use of AI-assisted workflows for coding, debugging, and test development.
• Equal employment consideration and ethical hiring practices.