Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
Пожаловаться
Зарплата и рынок
ЗП не указана
На похожих ролях по рынку
$156к$168кмедиана$187к
50 в выборке
На СНГ рынке: $2.5к/мес ($1.9к - $3.1к)
82
Хорошая вакансия
развернуть
В Company hidden чётко описана senior-позиция в ASIC-верификации с актуальным стеком, но требование от 12 лет опыта и разрешения на работу в США заметно сужает круг доступных вакансий.
Кликните для подробной информации
Высокий порог входаАктуальный стекКрупный игрокПонятные задачи
Оценка от Hirify AI
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Подключить Plus
Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Design Verification Engineer (ASIC): Developing and verifying SoC and embedded IP subsystems with an accent on SystemVerilog, UVM environments, coverage, assertions, and simulation analysis. Focus on designing verification components, building random and directed tests, debugging complex failures, and resolving verification trade-off scenarios.
Location: San Jose, California, United States; must have legal authorization to work in the US.
Company
hirify.global's ASIC Product Division develops SoC and embedded IP solutions and state-of-the-art subsystem designs for customer requirements.
What you will do
Develop verification environments using SystemVerilog and UVM.
Design UVM agents, behavioral models, and other verification components.
Implement coverage and assertions using SystemVerilog.
Develop random and directed test cases against specifications.
Analyze and debug simulation failures and coverage results.
Collaborate with verification and design teams on system and sub-block verification.
Requirements
Bachelor’s degree in Electrical and Electronic Engineering, Computer Science, or equivalent.
12+ years of relevant industry work experience.
Experience verifying designs at system and block level.
Fluent knowledge of RTL verification methodologies, including SystemVerilog.
Strong experience with ASIC design verification flows and DV methodologies.
Strong working knowledge of object-oriented verification languages such as OVM and UVM, plus C/C++, Perl, and scripting.
Strong independent design-debugging capability and the ability to analyze and resolve complex verification trade-off scenarios.
Strong verbal and written communication skills and comfort working in a team environment.
Demonstrated technical capability as a productive individual contributor in system and sub-block level verification.
Legal authorization to work in the United States.
Nice to have
Hardware design and debug experience, including C++/SystemC and other programming languages.
Experience with emulators and FPGA-based prototyping.
Familiarity with overall chip design methodologies and tools.
Knowledge of CPU, DDR, bus protocol, network protocol, or DSP design.
Culture & Benefits
High-performance design team environment involving verification and design teams.
Medical, dental, and vision plans.
401(k) participation with company matching, ESPP, EAP, paid holidays, paid sick leave, vacation, and applicable paid family and other leaves.
Eligibility for a discretionary annual bonus, competitive new-hire equity grants, and annual equity awards subject to plan documents and award agreements.
Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →