Senior Principal Engineer, Hardware Application Engineering — Signal Integrity & Power Integrity

Location: Santa Clara, CA, United States; travel to customer sites, ODMs, and labs as needed.

Expected base pay: $177,820–$266,400 per annum, plus eligibility for bonus and equity plans.

Company

hirify.global develops semiconductor solutions and silicon for enterprise, cloud, AI, networking, connectivity, and carrier infrastructure.

What you will do

• Act as the senior SI/PI technical authority for customer platforms using hirify.global Ethernet Switch and UALink silicon, from early channel definition through mass-production qualification.
• Define and drive adoption of high-speed SerDes, power delivery network, analog-interface, layout, routing, and stack-up guidelines with customers, ODMs, and internal teams.
• Perform post-silicon channel extraction, full-channel simulation, what-if analysis, PDN simulation, and design-fix recommendations.
• Lead compliance testing, lab characterization, customer bring-up, and production-ramp debugging using VNAs, BERTs, oscilloscopes, TDR equipment, jitter analyzers, and compliance test kits.
• Provide SerDes tuning guidance, develop SI/PI training, and support reference-platform definition and validation.
• Partner with silicon, packaging, board/system hardware, software, operations, customer, and ODM teams to improve products, roadmaps, and customer-facing solutions.

Requirements

• Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
• 15+ years of experience in hardware design, development, and validation of high-speed networking or compute systems.
• 10+ years of focused signal integrity and power integrity experience on high-speed SerDes platforms from 25G NRZ through 112G/224G PAM4.
• Expertise across the full SI lifecycle, including channel modeling and budgeting, layout and stack-up guidelines, post-layout extraction and simulation, design-fix recommendations, compliance, and tuning guidance.
• Ability to independently run and review PDN simulations covering impedance, IR drop, decoupling, transient response, and droop.
• Fluency with Ansys HFSS/SIwave, Cadence Sigrity/Clarity/PowerSI, or equivalent SI/PI EDA toolchains.
• Hands-on expertise with VNAs, BERTs, real-time and sampling oscilloscopes, TDR, jitter analyzers, and high-speed compliance test kits, including customer and internal lab debugging.
• Customer-facing experience resolving complex technical and real-world deployment issues; ability to communicate with senior customer engineers, ODM engineers, and cross-disciplinary stakeholders.
• Ability to develop and deliver technical training to engineering audiences.
• Applicants must be eligible to access export-controlled information under U.S. law; applicants other than U.S. citizens, lawful permanent residents, or protected individuals may require export license review.

Nice to have

• Direct experience with Ethernet switch platforms and/or open AI fabric standards and architectures.
• Experience supporting SI/PI for megascale data center platforms at production volume.
• Experience defining reference-platform SI/PI and enabling customers for silicon-based solutions.
• Familiarity with ODM/CM design and qualification flows, including DFM/DFT, reliability testing, and high-volume manufacturing variability.
• Experience defining SerDes tuning methodologies and correlating simulation, lab, and field-telemetry data.
• Familiarity with chip-to-module, copper cable, and connector ecosystems for high-speed Ethernet and AI fabric channels.
• Track record of influencing silicon and platform roadmaps using SI/PI insights from customer and field deployments.
• Candidates with fewer years of experience may be considered when they demonstrate equivalent mastery through impactful projects, deep technical contributions, or industry recognition.

Culture & Benefits

• Senior individual-contributor role with high customer and ODM visibility and technical leadership responsibility.
• Mentoring and training responsibilities across customers, ODMs, and internal engineering teams.
• Employee stock purchase plan with a two-year lookback, bonus and equity plans, and new-hire and annual equity refreshers.
• Family support programs, mental and physical health resources, recognition and service awards, and benefits supporting employees through retirement.

Hiring process

• Interviews evaluate individual experience, thought process, and communication in real time.
• AI tools, transcription apps, automated answer generators, and automated note-taking bots are not permitted during interviews.