System Signal/Power Integrity Engineer (High-Speed SerDes)

Location: San Jose, California, United States; onsite

Company

hirify.global develops semiconductor and connectivity technologies.

What you will do

• Support high-data-rate SerDes applications for systems up to 400G and perform system-level signal and power integrity design trade-offs and debugging.
• Collaborate with package, PCB, silicon, and customer engineers on measurement-simulation correlation, design requirements, and deliverables.
• Develop electromagnetic and circuit models using Ansys HFSS, SIWave, Q3D, Polar, and Keysight ADS for pre-layout and post-layout package and PCB simulations.
• Perform 50GHz+ VNA/TDR measurements and capture high-fidelity laboratory data using sampling and real-time oscilloscopes, spectrum analyzers, and optical oscilloscopes.
• Evaluate package, PCB, material, connector, and laminate solutions while balancing reliability, cost, complexity, and simulation-model accuracy.
• Document requirements, project plans, models, simulation results, correlation investigations, and best practices; support customer analysis and debug.

Requirements

• BS with 12+ years, MS with 10+ years, or PhD with 7+ years in Electrical Engineering or Physics.
• Experience in one or more of signal integrity for high-speed digital applications, electromagnetic transmission-line theory, microwave theory, numerical field-solver theory, power integrity, IC package design, or photonics.
• Knowledge of high-speed data communications, transmission-line and electromagnetic-field theory, numerical analysis, VNA/TDR measurements, and time- and frequency-domain analysis.
• Experience with bit-by-bit and statistical simulators for SerDes links, including insertion loss, return loss, crosstalk, BER, jitter, statistical eye diagrams, and phase-noise analysis for PLLs, reference clocks, and SerDes TX-RX links.
• Understanding of laminate design and fabrication limitations for package and PCB designs, optical/electrical engine concepts, CWDM, OMA, chromatic dispersion, and four-wave mixing.
• Knowledge of power integrity concepts, including PDN impedance analysis and design, ultra-low-impedance measurements, SMT capacitor performance metrics, and CPA and/or SI-Wave for PDN simulations.
• Ability to organize multiple projects, develop and track project plans, communicate complex concepts, and document applicable ASIC package and PCB requirements based on industry standards, customer requirements, and internal performance goals.
• Experience with EM modeling tools including Ansys HFSS, SIWave, Q3D, and Polar, and circuit simulation with Keysight ADS.

Nice to have

• Experience with Matlab.
• Experience with Cadence APD/Allegro and other layout tools.
• Experience with Linux.
• Experience with Keysight AEL.

Culture & Benefits

• Full-time employment in San Jose, California.
• Annual discretionary bonus and competitive new-hire and annual equity awards, subject to applicable plans and agreements.
• Medical, dental, and vision plans.
• 401(k) participation with company matching, ESPP, EAP, paid holidays, paid sick leave, vacation, and applicable family and other leaves.
• Equal opportunity employment consistent with applicable federal, state, and local laws.