Design-for-Test (DFT) Engineer (ASIC)

Location: Mountain View, United States; hybrid

Company

hirify.global is an applied AI company building foundational hardware and software for the semiconductor industry, critical AI infrastructure, and broader systems infrastructure.

What you will do

• Own chip-level DFT architecture, including scan insertion, ATPG, scan compression, MBIST, boundary scan/JTAG, and test access infrastructure.
• Drive DFT insertion and integration across RTL, synthesis, and physical design while balancing power, performance, and area.
• Lead DFT verification, ATPG pattern generation, fault coverage analysis, test-mode validation, and signoff through tapeout.
• Deliver production-ready test patterns and test collateral for manufacturing partners, ATE integration, silicon bring-up, and diagnosis.
• Establish scalable DFT flows, automation, and methodology using industry-standard EDA tools.
• Define requirements for external DFT partners, oversee outsourced work, and review deliverables with RTL, verification, physical design, and silicon product engineering teams.

Requirements

• 7+ years of experience in DFT implementation for complex ASICs or SoCs, including successful tapeouts.
• Hands-on expertise in scan insertion, ATPG, scan compression, fault coverage analysis, and test pattern generation.
• Experience with MBIST, boundary scan/JTAG, and DFT integration across RTL and gate-level designs.
• Proficiency with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX, or Cadence Modus.
• Understanding of RTL design, synthesis, static timing analysis, and physical design considerations.
• Experience delivering manufacturing test patterns and collaborating with silicon product engineering or ATE teams.
• Strong scripting skills in Python, Tcl, or similar languages.
• Ability to independently own DFT architecture, drive cross-functional technical decisions, and communicate across design, verification, and product engineering teams.

Nice to have

• Experience establishing DFT architecture and methodology from the ground up for a new ASIC program.
• Familiarity with IEEE 1500, IEEE 1687 (IJTAG), hierarchical DFT, and advanced scan compression techniques.
• Experience with memory redundancy, built-in self-repair (BISR), silicon diagnosis, and yield improvement.
• Experience working with external DFT implementation partners or managing outsourced DFT deliverables.
• Exposure to AI accelerators, memory-intensive architectures, or unconventional computing systems.
• Experience using AI-assisted or agentic tools to automate silicon design and verification workflows.

Culture & Benefits

• Hybrid work based in Mountain View.
• Collaboration across offices in New York City, Silicon Valley, London, Copenhagen, and Seoul.
• Inclusive environment with equal employment opportunity and reasonable accessibility accommodations.