DFT Engineer (AI)

Location: Palo Alto Office, USA

Company

hirify.global develops world models and agents for understanding and building hardware, electronics systems, and semiconductors with AI.

What you will do

• Define DFT architecture for SoCs and IP, including scan, compression, MBIST, LBIST, and boundary scan.
• Insert and verify DFT logic and generate ATPG patterns that meet coverage targets.
• Collaborate with RTL, synthesis, and physical design teams to close DFT timing and area impact.
• Support silicon bring-up, pattern debugging, and yield analysis with test and product engineering.
• Build automation for DFT flows and coverage reporting.
• Help define how AI can accelerate DFT insertion and pattern generation.

Requirements

• 5+ years of DFT experience on production tapeouts.
• Hands-on experience with Tessent, TestMAX, or Modus.
• Strong knowledge of scan, compression, ATPG, MBIST, and IEEE 1149.1/1687.
• Experience with DFT verification and gate-level simulation.
• Experience with Tcl and Python scripting.

Nice to have

• Post-silicon test bring-up and ATE experience.
• Experience with 2.5D/3D or chiplet test strategies.
• Interest in AI-assisted design tools.

Culture & Benefits

• Full-time position within the Chips & Silicon department.
• Work with leading semiconductor companies on real silicon programs.
• Collaborate with a team backed by Silicon Valley investors, Stanford University, and semiconductor industry leaders.