Senior ASIC Design Engineer (PCIe)

Location: Remote for employees residing within the United States; department location listed as San Jose, California.

Company

hirify.global develops high-performance scale-out networking hardware and software for AI and HPC data centers, integrating silicon, software, and system-level technologies.

What you will do

• Own end-to-end integration of PCIe IP into complex ASIC and next-generation SoC designs.
• Collaborate with IP vendors, architecture, verification, physical design, board, firmware, and software teams.
• Optimize PCIe performance across PHY tuning, DMA, and transaction-layer efficiency.
• Contribute to IO and interconnect architecture and microarchitecture for scalable high-performance compute platforms.
• Lead lab-based silicon bring-up, PCIe link validation, compliance, and interoperability testing.
• Debug functional and performance issues at RTL, gate-level, and silicon, while mentoring junior engineers and defining development practices.

Requirements

• BS/MS in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of industry experience in ASIC/SoC design focused on PCIe controller integration.
• Proven experience with silicon bring-up and high-speed interface debugging.
• Solid understanding of the PCIe protocol stack, including PHY, MAC, TLP, DLL, configuration space, and link training.
• Hands-on experience with PCIe verification environments, performance tuning, and power-aware design.
• Familiarity with PCIe compliance testing, VCS or Questa simulation tools, and lab equipment such as protocol analyzers and oscilloscopes.
• Strong scripting and debugging skills using Python, Perl, and TCL.
• Strong verbal and written communication skills.
• Good understanding of high-bandwidth, low-latency connectivity for high-performance compute platforms.

Nice to have

• Experience with PCIe Gen5/Gen6 and advanced retimer or switch solutions.
• Exposure to CXL, CCIX, or other cache-coherent interconnects.
• Background in data center or AI/ML accelerator architectures.
• Experience with ZeBu, Palladium, HAPS, or similar emulation and prototyping platforms for PCIe subsystem validation.

Culture & Benefits

• Work in a fast-growing, forward-thinking organization developing AI and HPC networking solutions.
• Flexible remote work environment with collaboration across a global organization spanning six countries and multiple U.S. states.
• Compensation package including base pay, equity, cash, and performance-based incentives.
• Medical, dental, vision, disability, life, dependent care, accidental injury, and pet insurance.
• Paid holidays, sick time, bonding leave, pregnancy disability leave, and Open Time Off for regular full-time exempt employees.
• 401(k) plan with company match.