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4 дня назад

Logic Design Engineer (SoC/RTL)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Malaysia
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Logic Design Engineer (SoC/RTL): Developing and integrating RTL/IP for next-generation Client SoC platforms with an accent on power intent, clock and power-domain handling, and front-end design quality. Focus on solving power convergence issues, validating integration readiness, and coordinating RTL, verification, synthesis, timing, and formal equivalence activities.

Location: On-site in Penang, Malaysia

Company

hirify.global develops next-generation Client SoC products and platforms.

What you will do

  • Own internal IP RTL design and development or integrate high-performance, high-bandwidth IP into Client SoC platforms.
  • Define, implement, and deliver IP features, change requests, and enhancements.
  • Drive IP-to-SoC handoff quality, design completeness, compliance, and downstream integration readiness.
  • Perform RTL and logic integration, including power intent definition, signal handling across power planes and clock domains, and delivery of front-end collateral.
  • Collaborate with verification teams to validate functionality, features, and integration readiness.
  • Execute RTL quality checks covering static analysis, synthesizability, timing and power convergence, netlist quality, and formal equivalence verification; investigate power issues and recommend design or flow solutions.

Requirements

  • Bachelor’s or Master’s degree in Electrical and Electronic Engineering, Computer Engineering, Computer Science, or a related discipline, with at least 3 years of experience in IP or SoC RTL/Logic Design.
  • Knowledge of IP or subsystem architecture, I/O architecture, and industry-standard high-speed bus protocols.
  • Knowledge of SoC/ASIC design methodology and industry-standard front-end development practices.
  • Knowledge of SoC fabric and interconnect design.
  • Experience with RTL design using Verilog and SystemVerilog.
  • Experience with industry front-end and RTL tools, flows, and design methodologies.
  • Experience using AI tools or AI-assisted engineering workflows for RTL/Logic development productivity, including design exploration, code generation, review, debugging, documentation, and front-end quality checks.
  • Ability to combine domain expertise, automation, scripting, AI-assisted tools, and structured engineering practices to accelerate delivery while maintaining design quality.
  • Pre-silicon or post-silicon lab debugging and power-on experience, plus excellent communication, collaboration, problem-solving, and teamwork skills.

Culture & Benefits

  • Full-time experienced-hire position.
  • On-site work model in Penang, Malaysia.
  • Shift 1 schedule in Malaysia.
  • Ethical hiring practices with no recruitment, medical examination, or other hiring fees.

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