Staff Logic Design Engineer (AI)

Location: On-site in Penang, Malaysia

Company

hirify.global develops next-generation Client SoC products and semiconductor technologies used worldwide.

What you will do

• Own internal IP RTL design and development or integrate high-performance, high-bandwidth IP into Client SoC platforms.
• Define, implement, and deliver IP features, change requests, and enhancements.
• Drive IP-to-SoC handoff quality, ensuring design completeness, compliance, and downstream integration readiness.
• Perform RTL and logic integration, including power intent, signal handling across power planes and clock domains, and front-end collateral delivery.
• Collaborate with verification teams to validate functionality, features, and integration readiness.
• Execute front-end quality checks covering static analysis, synthesis, timing and power convergence, netlist quality, and formal equivalence verification.

Requirements

• Bachelor’s or master’s degree in electrical and electronic engineering, computer engineering, computer science, or a related discipline.
• At least 3 years of experience in IP or SoC RTL/logic design.
• Knowledge of IP and subsystem architecture, I/O architecture, high-speed bus protocols, SoC/ASIC methodologies, or SoC fabric and interconnect design.
• Hands-on RTL design experience with Verilog and SystemVerilog, plus industry front-end tools and flows.
• Experience with AI tools or AI-assisted engineering workflows for design exploration, code generation, review, debugging, documentation, or quality checks.
• Strong communication, collaboration, problem-solving, and teamwork skills; pre-silicon or post-silicon lab debug and power-on experience is relevant.

Culture & Benefits

• Full-time employment with an experienced-hire classification.
• Shift 1 working schedule aligned with Malaysia.
• On-site work model in Penang.
• Hiring follows responsible business and ethical recruitment practices; recruitment and medical examination fees are not charged to candidates.