Design Verification Engineer (FPGA/ASIC)

Location: Penang, Malaysia; onsite. Right to work in Malaysia is required.

Company

hirify.global develops low-cost, low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices.

What you will do

• Verify IP blocks and full-chip FPGA/ASIC designs.
• Define test plans and develop SystemVerilog/UVM testbenches and test content.
• Debug verification failures and run regressions to deliver high-quality design validation.
• Collaborate with architects, RTL designers, DFX engineers, and automation engineers on verification coverage and quality signoff.

Requirements

• Bachelor’s degree in Electronic Engineering or a related field.
• At least 2 years of experience in the semiconductor or related industry.
• Familiarity with protocols and technologies including Ethernet, PCIe, JESD, CPRI, DDR, Video IP, and FPGA technologies.
• Experience with test planning, testbench development, stimulus generation, reference models, assertion-based verification, and functional coverage.
• Successful background and reference checks and satisfactory proof of the right to work in Malaysia.

Nice to have

• Experience with SystemVerilog, UVM, constrained-random verification, and assertion-based methodologies.

Culture & Benefits

• Fast-paced, results-oriented, team-first working environment.
• Collaborative atmosphere focused on R&D, product innovation, customer service, and customer success.
• Comprehensive compensation and benefits program.
• Inclusive workplace that values diverse individuals, ideas, perspectives, insights, and values.