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5 дней назад

Staff Design Verification Engineer (FPGA/ASIC)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior/lead
Английский
b2
Страна
Malaysia
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Staff Design Verification Engineer (FPGA/ASIC): Leading functional verification planning, execution, and sign-off for complex FPGA/ASIC IPs, subsystems, and SoC-level designs with an accent on SystemVerilog, UVM, coverage, and verification infrastructure. Focus on architecting reusable verification environments, debugging RTL and gate-level issues, driving closure, and mentoring verification engineers.

Location: Penang, Malaysia. Satisfactory proof of the right to work in Malaysia is required.

Company

hirify.global develops low-cost, low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices.

What you will do

  • Lead verification planning, execution, and sign-off for complex FPGA/ASIC IPs, subsystems, and SoC-level designs.
  • Define verification methodologies, test strategies, coverage goals, and closure criteria.
  • Architect and develop SystemVerilog/UVM environments, reusable verification components, scoreboards, assertions, and coverage models.
  • Drive functional and code coverage closure, regression analysis, risk assessment, and debugging of RTL, integration, low-power, timing, and gate-level simulation issues.
  • Collaborate with architects, RTL designers, validation engineers, firmware teams, and program managers on product execution.
  • Provide technical leadership, mentor verification engineers, support silicon bring-up and failure analysis, and improve verification productivity and reusability.

Requirements

  • Bachelor's or Master's degree in Electrical/Electronic Engineering, Computer Engineering, or a related field.
  • 8+ years of ASIC/FPGA functional verification experience.
  • Strong expertise in SystemVerilog, UVM, and assertion-based verification.
  • Proven experience leading verification of complex IPs, subsystems, or SoCs from planning through sign-off.
  • Strong debugging skills in RTL, gate-level, and system-level verification environments.
  • Experience with constrained-random verification, coverage-driven verification, and regression management.
  • Proficiency in Python, Perl, Shell, or other scripting languages.
  • Excellent communication and cross-functional collaboration skills.

Nice to have

  • Experience with PCIe, USB, MIPI CSI/DSI, Ethernet, SerDes, or similar high-speed protocols.
  • Experience with low-power verification using UPF/CPF.
  • Experience with GLS, timing validation, and post-silicon debugging.
  • Experience driving verification methodology and infrastructure improvements across multiple projects.
  • Ability to mentor engineers and lead technical initiatives.

Culture & Benefits

  • Fast-paced, results-oriented environment with a team-first and collegial culture.
  • International engineering, design, manufacturing, sales, marketing, and support organization.
  • Comprehensive compensation and benefits program.
  • Commitment to diversity and inclusion.

Hiring process

  • Successful background and reference checks are required.
  • Satisfactory proof of the right to work in Malaysia is required.

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