aiateyield analysissemiconductor testingwafer sortsilicon bring upmanufacturing testfinal package test
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Зона ответственности охватывает весь цикл тестирования чипов, а результаты первого года описаны конкретно; ниша AI-железа добавляет техническую глубину.
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Hirify AI/Оригинал
TL;DR
Senior Semiconductor Test Engineer (AI): Building and releasing production test flows for AI inference processors across silicon bring-up, Wafer Sort, Final Package Test, characterization, and high-volume manufacturing with an accent on analog behavior, process variation, trim, calibration, and digital coverage. Focus on developing ATE programs, translating test patterns, analyzing yield and manufacturing data, and driving systematic failures to root cause during production ramp.
Location: Austin, TX; hybrid
Company
Develops AI inference processors based on analog compute-in-memory architecture.
What you will do
Own end-to-end production test strategy across Wafer Sort, Final Package Test, characterization, screening, and volume ramp.
Develop, debug, release, optimize, and sustain test programs and infrastructure for new silicon products.
Define test methodology, coverage strategy, screening philosophy, release criteria, and tradeoffs across coverage, cost, test time, quality, and ramp schedule.
Lead silicon bring-up, characterization, correlation, guardbanding, and test transfer into manufacturing.
Analyze yield and quality data, identify systematic failures and escapes, and drive root-cause resolution.
Work with OSATs, foundries, ATE vendors, design, DFT, product engineering, reliability, and manufacturing teams.
Requirements
5+ years of experience in semiconductor test engineering, product engineering, or production test development.
Hands-on ownership of Wafer Sort and Final Package Test.
Experience developing, debugging, and releasing production test programs on ATE platforms.
Experience converting and translating STIL, WGL, and VCD test patterns into ATE-specific formats.
Strong knowledge of manufacturing test flows, device screening, test coverage, guardbanding, and outgoing quality.
Experience taking silicon through bring-up, characterization, yield ramp, and production release.
Strong debug skills and fluency with manufacturing test data.
Experience collaborating with design, DFT, product, reliability, and operations teams.
Nice to have
Experience testing mixed-signal or analog silicon, including trim and calibration.
Experience with AI, accelerator, or high-performance compute silicon.
Experience with Advantest, Teradyne, or similar ATE platforms.
Experience with probe cards, load boards, hardware interfaces, and test hardware debug.
Experience with DFT structures such as scan, MBIST, and boundary scan.
Experience managing OSATs and other external manufacturing partners.
Experience with scripting, automation, and test-data analysis, including Python, JMP, or yield-analysis tools.
A track record of reducing test time and improving yield and correlation during ramp.
Culture & Benefits
Collaborative and respectful work environment.
Tools and support to deliver meaningful work.
Values professionalism, creativity, integrity, and inclusion.
Wide range of experiences and perspectives across the team.
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