Senior IC Packaging Engineer (AI)

Location: San Jose, CA, United States

Company

hirify.global is a fast-growing, well-funded semiconductor startup building AI infrastructure security and management products based on its Trusted Control/Compute Unit and Platform Efficiency Controller.

What you will do

• Provide technical leadership and architectural ownership for IC and System-in-Package packaging across multiple products and programs.
• Define package architectures and technology roadmaps covering 2D, RDL-based fan-out (2.5D), chiplet-based designs, silicon interposers, and heterogeneous integration.
• Lead package design and physical layout for high-speed SerDes/PHY, PCIe, CXL, LPDDR5, UCIe, and other multi-gigabit interfaces.
• Define substrate stack-ups, materials, bump/RDL architectures, and DFM guidelines while driving SI/PI, thermal, mechanical, reliability, cost, yield, schedule, and risk trade-offs.
• Lead collaboration with OSATs, foundries, substrate suppliers, and cross-functional design, product, test, operations, reliability, and customer teams from technology path finding through production ramp.
• Establish scalable design methodologies, best practices, reusable packaging flows, and long-term packaging strategy.

Requirements

• BSEE or MSEE in Electrical Engineering or a related field; a PhD is a plus.
• At least 10 years of extensive IC packaging experience for SoCs, ASICs, or memory products.
• Deep hands-on expertise in Flip-Chip BGA, System-in-Package, RDL, silicon interposers, and chiplet architectures using UCIe.
• Strong understanding of electrical, mechanical, thermal, and reliability trade-offs; advanced packaging materials and substrate technologies; DFM; and yield optimization.
• Technical leadership of multiple end-to-end packaging programs from early architecture through high-volume production.
• High-speed SerDes package development experience, including PCIe Gen5, LPDDR5 or LPDDR5X, USB 3.x, or 10G interfaces.
• Experience defining die-to-die and chiplet-based RDL and bump architectures.
• Direct collaboration with OSATs, foundries, and substrate suppliers for co-development and production ramp.
• Strong cross-functional leadership and the ability to operate autonomously, make high-impact decisions, and execute in a startup environment.
• Clear understanding of cost, yield, schedule, and risk trade-offs at product and portfolio levels.

Nice to have

• Experience with Cadence Allegro Package Designer or equivalent EDA tools.
• SI/PI expertise, including S-parameter extraction and PDN optimization using HFSS, SIwave, or Ansys Designer.
• Experience building new packaging methodologies or platforms from scratch.

Culture & Benefits

• Fast-growing, well-funded startup environment with more than 180 people worldwide.
• Every employee holds equity in the company.
• Culture emphasizes persistence, curiosity, continuous learning, hard and smart work, and mutual support.
• Diverse and multifaceted work environment with equal-opportunity employment practices.
• Headquarters in Silicon Valley with access to leading research, technology, and talent.