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8 дней назад

Platform Integration Engineer (SystemVerilog)

164 470 - 232 190$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Platform Integration Engineer (SystemVerilog/RTL): Developing and integrating IP blocks and subsystems into full-chip designs with an accent on logic design, microarchitecture, verification, and power-performance-area optimization. Focus on implementing AMBA and coherent protocols, resolving RTL and physical integration challenges, and supporting reliable IP-to-SoC handoff.

Location: Hybrid role based at the hirify.global site in Santa Clara, California, United States, with time split between on-site and off-site work.

Annual salary: $164,470–$232,190 USD.

Company

hirify.global's Central Engineering Group develops and validates silicon IP and engineering solutions for hirify.global's technology portfolio and semiconductor products.

What you will do

  • Develop RTL logic designs and simulations for IP blocks and subsystems integrated into full-chip designs.
  • Define architecture and microarchitecture features and implement them in the design.
  • Optimize logic for power, performance, area, and timing while maintaining physical implementation integrity.
  • Review verification plans, resolve RTL test failures, and validate design features.
  • Collaborate with physical design teams on floorplan limitations and seamless design integration.
  • Drive quality assurance compliance for IP-to-SoC handoff.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field plus 6+ years of RTL design and SystemVerilog experience, or a relevant master's degree plus 4+ years of RTL design and SystemVerilog experience.
  • Experience with industry-standard front-end design tools, including synthesis, static timing analysis, and lint checks.
  • Experience with AMBA protocols and coherent protocols such as IDI or CHI.
  • Knowledge of hardware design concepts including logic design, state machines, and network-on-chip architectures.
  • Ability to collaborate across cross-functional and geographically distributed teams.
  • Strong attention to detail when reviewing verification plans and resolving design failures.
  • Passion for innovation and continuous improvement in a fast-paced engineering environment.

Nice to have

  • Experience with high-speed interconnect designs and power-performance optimization.
  • Proficiency in Python, Perl, or Tcl for scripting automation.
  • Demonstrated collaboration with cross-functional and geographically distributed groups.

Culture & Benefits

  • Collaborative and inclusive engineering environment.
  • Competitive pay, stock bonuses, health benefits, retirement benefits, and vacation.
  • Hybrid work model combining on-site and off-site work.
  • Shift 1 schedule in the United States of America.

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