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8 дней назад

Principal Engineer-Design (SoC Integration and RTL/IP)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Principal Engineer-Design (SoC Integration and RTL/IP) (SoC/RTL/FPGA): Leading SoC integration, synthesizable RTL and reusable IP development for dsPIC microcontrollers with an accent on AMBA protocols, clock/reset architecture, timing closure, and FPGA prototyping. Focus on integrating processors, memories, peripherals, and custom IP, solving CDC/RDC and chip-level design issues, and driving post-silicon debug and technical leadership.

Location: Chandler, Arizona, United States. Full-time, on-site role. Monday–Friday, 8 hours per day; travel expected 0%–25%.

Company

hirify.global is a large semiconductor technology company developing microcontrollers, integrated circuits, and hardware solutions.

What you will do

  • Lead top-level and subsystem integration of processors, memories, peripherals, and custom IPs.
  • Integrate IP using proprietary bus interfaces and AMBA AXI, AHB, and APB protocols.
  • Implement clock/reset integration, interrupt routing, address mapping, and pad/pin connectivity.
  • Develop synthesizable SystemVerilog RTL, reusable peripherals, controllers, wrappers, and power-management modules.
  • Resolve lint, synthesis, timing, CDC, and RDC issues; support timing optimization, design debug, and ECO revisions.
  • Lead design reviews, collaborate across architecture, verification, DFT, physical design, firmware, and systems teams, and mentor junior engineers.

Requirements

  • Bachelor’s degree in electrical engineering, electronics engineering, computer engineering, computer science, physics, or a related field, with 10+ years of ASIC/SoC design, RTL, FPGA, or SoC integration experience.
  • Strong knowledge of SystemVerilog and AMBA AXI/AHB/APB protocols.
  • Experience with SoC integration, IP development, clock/reset architecture, and memory mapping.
  • Hands-on experience with Vivado or Quartus, synthesis, static timing analysis, and timing closure.
  • Familiarity with QuestaSim, VCS, or Xcelium, plus CDC/RDC analysis, RTL lint, and Python/Tcl scripting.
  • Work is performed on-site in Chandler, Arizona, United States.

Nice to have

  • Experience with ARM- or RISC-V-based SoCs and Ethernet, USB, SPI, I2C, or UART interfaces.
  • Knowledge of low-power design, DFT integration, and formal-based verification.
  • Experience with FPGA synthesis, place and route, timing closure, constraints, and FPGA-based validation.
  • Bachelor’s or master’s degree in electronics, electrical engineering, VLSI, or a related field.

Culture & Benefits

  • Work within a large global organization focused on semiconductor and embedded technology.
  • Culture emphasizing trust, empowerment, respect, diversity, communication, and professional development.
  • Leadership development programs and opportunities for employee growth.
  • Indoor work environment with approximately 85% of the workday spent sitting.

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