pythonperlphysical designedatclstatic timing analysisplace and routesignoff
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
$148к-276к/год
$170к$210кмедиана$230к
По похожим ролям (50) ~ $210к/год
На СНГ рынке: $2.5к/мес ($1.9к - $3.1к)
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Чётко очерченная senior-позиция в крупной EDA-компании даёт глубокий опыт в передовых разработках микросхем и работе над продуктом с учётом запросов клиентов, но сочетает техническую экспертизу с общением с заказчиками и продвижением решений.
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Техническая и клиентская рольПередовой секторСильный игрок рынка
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Physical Design and Signoff, Sr. Principal AE (Digital Implementation and Signoff): Supporting leading-edge customers with Cadence synthesis, place-and-route, and signoff technologies to achieve PPA targets and faster design closure with an accent on advanced-node physical design, timing and power closure, and customer-facing technical leadership. Focus on guiding technical evaluations, improving implementation flows with Tcl or other programming skills, collaborating with R&D, and driving adoption of Cadence EDA tools.
Location: San Jose, United States of America
Annual salary: $148,400–$275,600 in California. Incentive compensation, including bonus, equity, and benefits, may also be available.
Company
hirify.global develops technologies for digital design implementation, signoff, and electronic design automation.
What you will do
Provide technical support to customers in backend digital design implementation and signoff, including place and route, design closure, and timing and power signoff.
Guide customers in using hirify.global technologies to meet design goals and project schedules.
Conduct technical presentations, product demonstrations, and technical evaluations or benchmarks.
Collaborate with R&D to improve tools and methodologies in line with customer requirements.
Drive adoption and proliferation of hirify.global tools and technologies.
Amend and augment implementation flows with Tcl or other programming skills, and capture best practices from evaluations and benchmarks.
Requirements
10+ years of industry experience in Physical Design.
Strong knowledge of digital design fundamentals, semiconductor fundamentals, and Static Timing Analysis.
Experience with IC digital implementation flows and backend EDA tools, including Place and Route, IR Drop, backend design timing, and power closure.
Experience with advanced nodes at 10nm and below.
Experience with scripting languages such as Tcl, Perl, or Python.
Strong customer-facing communication and problem-solving skills, including strong verbal, written, and customer communication skills.
Strong personal drive for continuous learning and expanding professional skill sets.
BS degree in Computer Science, Engineering, Electrical Engineering, or a related field.
Nice to have
MS degree in Computer Science, Engineering, Electrical Engineering, or a related field.
Experience with frontend IC digital implementation flows and EDA tools, including Synthesis, DFT, and Logical Equivalence Checking.
Experience with hirify.global tools such as Genus, Innovus, Conformal, Tempus, Modus, or Voltus, or with ICC, ICC2, DC, or PrimeTime.
Experience with advanced nodes at 5nm and below.
Culture & Benefits
Paid vacation and paid holidays.
401(k) plan with employer match.
Employee stock purchase plan.
Medical, dental, and vision plan options.
Potential bonus, equity, and other incentive compensation.
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