Physical Design Engineer (AI/Semiconductors)

Location: Palo Alto Office, USA

Company

hirify.global develops world models and agents for understanding and building hardware, electronics systems, and semiconductors with AI.

What you will do

• Own block-level and full-chip physical implementation from netlist to GDSII, including floorplanning, placement, clock tree synthesis, and routing.
• Drive timing, power, and congestion closure with synthesis and static timing analysis teams.
• Close physical verification and power-integrity requirements for signoff, including DRC/LVS, IR drop, and electromigration.
• Build and improve place-and-route flows and automation using Tcl and Python.
• Evaluate AI-generated floorplans and implementation decisions and help define quality standards.
• Work directly with customer teams on implementation challenges.

Requirements

• 5+ years of physical design experience with multiple production tapeouts.
• Deep experience with Innovus or Fusion Compiler/ICC2.
• Strong understanding of timing closure, clock tree synthesis, and power distribution networks.
• Experience at advanced nodes of 7nm and below.
• Strong Tcl and Python scripting skills.

Nice to have

• Full-chip integration or hierarchical design experience.
• Experience with high-speed or low-power designs.
• Interest in applying AI or machine learning to physical design.

Culture & Benefits

• Work on real silicon programs with leading semiconductor companies.
• Collaborate with a team of semiconductor, AI, hardware, and physical-design experts.
• Contribute to teaching AI how expert physical designers make implementation decisions.
• Work from the Palo Alto office.